Full Job Description
Micron's High Bandwidth Memory (HBM) Design Architecture team develops memory solutions for AI accelerators, high-performance computing, and data centers. Our Roadmap and Pathfinding group operates at the intersection of device technology, process, packaging, and product architecture, with a mission to enable next-generation memory technologies for product intercept.
As an HBM Design Architect, you will lead the technical enablement of novel memories and integration technologies - such as DRAM, gain-cell memory, stacked DRAM, and scaled-pitch hybrid bonding - grounded in a deep understanding of mainstream DRAM and HBM products. You will translate technology capabilities into product architectures, identify critical product requirements at risk, and drive de-risking plans with design, process, packaging, and product teams!
Responsibilities
• Lead architecture and feasibility assessments for emerging memories (DRAM, gain cell, stacked/vertical DRAM) and advanced integration (hybrid bonding, fine-pitch TSV)
• Apply mainstream DRAM/HBM product knowledge - array architecture, timing parameters, bandwidth, power, RAS, and JEDEC requirements - to define what a new technology must deliver to be product-viable
• Translate device and process characteristics (retention, variability, cell/array physics, BEOL and bonding constraints) into product-level requirements for bandwidth, latency, power, thermals, density, and reliability
• Identify technology-product gaps, define technology targets, and drive de-risking plans including test vehicles, DOEs, and modeling/simulation strategies
• Partner with process integration, device, packaging, and design teams to define technology-to-product intercept points and decision criteria
• Lead system-technology co-optimization (STCO) studies spanning array architecture, periphery/CMOS-under-array, interconnect, PDN, and thermal trade-offs
• Develop roadmap proposals and present recommendations to technical leadership and cross-site working groups (LLM)
Minimum Qualifications
• BS in Electrical Engineering, Physics, Materials Science, or related field with 7+ years of relevant experience; MS with 5+ years; or PhD with 3+ years
• Solid grounding in mainstream DRAM and/or HBM product architecture and design (array, periphery, datapath, timing, power)
• Deep understanding of DRAM or emerging memory cell and array operation (sensing, retention, disturb, variability)
• Working knowledge of semiconductor process technology and its impact on device and circuit behavior
Preferred Qualifications
• PhD or equivalent experience with 10+ years in DRAM/HBM build, memory technology, or pathfinding
• Direct experience with vertically coordinated DRAM technologies, gain-cell structures (2T0C/IGZO or similar), stacked memory builds, or other emerging memory programs
• Experience with hybrid bonding, TSV-based 3D integration, or advanced packaging technology development
