Meta is seeking a Staff PCB Layout Engineer to drive the design and delivery of complex printed circuit boards for large-scale infrastructure hardware. In this role, you will define layout architecture and establish engineering standards for high-speed digital, power delivery, and signal integrity-critical designs that power Meta's data center and infrastructure platforms. You will partner with electrical engineers, mechanical engineers, and manufacturing teams to shape board-level design strategy from concept through mass production, ensuring reliability and performance at scale.
Responsibilities
Define PCB layout architecture and floorplanning strategies for complex, high-layer-count boards used in infrastructure and data center hardware
• Establish and own PCB design rules, constraints, and layout guidelines for high-speed interfaces including PCIe, DDR, Ethernet, and SerDes
• Lead signal integrity and power integrity analysis in collaboration with electrical engineering teams, driving layout decisions based on simulation results
• Drive design-for-manufacturability reviews with contract manufacturers and PCB fabricators to ensure yield, reliability, and cost targets are met
• Define and maintain organization-wide PCB layout standards, templates, and best practices adopted across infrastructure hardware programs
• Collaborate with mechanical engineers to resolve board-level packaging constraints, thermal management requirements, and enclosure integration challenges
• Provide technical guidance to other layout engineers across multiple concurrent infrastructure hardware programs
• Partner with supply chain and component engineering teams to evaluate and qualify alternative components and footprints
• Lead post-layout verification activities including design rule checks, electrical rule checks, and pre-production board bring-up support
• Evaluate and introduce new EDA tooling, layout methodologies, and fabrication technologies to improve design quality and cycle time
Minimum Qualifications
• 8+ years of experience in PCB layout design for high-speed digital systems, including boards with DDR, PCIe, or high-speed SerDes interfaces
• 8+ years of experience with industry-standard EDA layout tools such as Cadence Allegro, Mentor Xpedition, or equivalent
• Experience defining PCB stack-up configurations, impedance control strategies, and design rule constraints for high-layer-count boards
• Experience collaborating with signal integrity and power integrity teams to translate simulation results into layout implementation decisions
• Experience leading PCB layout efforts across the full product development lifecycle from schematic capture through manufacturing release
Preferred Qualifications
• Experience designing PCBs for data center infrastructure hardware including server, storage, or networking platforms
• Experience with high-speed (100Gbps+) signal interfaces
• Experience establishing layout centers of excellence or defining team-wide PCB design standards across multiple concurrent programs
• Experience with complex designs using custom ASICs
