BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field
2+ years of experience in design verification for FPGAs or ASICs
Proficiency in SystemVerilog for verification
Familiarity with verification methodologies like constrained randomization and functional coverage
Experience with simulation and debugging tools (e.g., VCS, Verdi)
Comfortable working in a Linux environment
Strong problem-solving, debugging, and communication skills
Responsibilities
Verify and maintain high-performance FPGA compute and networking systems
Contribute to the verification process from specification to coverage closure
Partner with design engineers to develop and execute comprehensive test plans
Create and maintain reusable verification components and testbenches in SystemVerilog
Utilize simulation and debugging tools to resolve design issues
Improve verification processes, tools, and methodologies
Benefits
Full-time on-site position in Needham, MA
Opportunity to work on cutting-edge FPGA and networking technologies
Collaborative environment with design engineers
Focus on continuous improvement in verification methodologies
Potential for professional growth in a dynamic field
Full Job Description
As a Hardware Engineer II - Design Verification at HPR, you will:
Verify and maintain high-performance FPGA compute and networking systems used in electronic trading
Contribute to the verification process from specification, test planning, and testbench development through execution and coverage closure
Partner with design engineers to develop, review, and execute comprehensive test plans
Create and maintain reusable verification components and testbenches written in SystemVerilog
Utilize simulation and debugging tools to identify, investigate, and resolve design issues
Contribute to improving our verification processes, tools, and methodologies
Required Qualifications
BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field
2+ years of experience in design verification for FPGAs or ASICs
Proficiency in SystemVerilog for verification
Familiarity with verification methodologies, including constrained randomization, functional coverage, and assertion-based checking
Experience with simulation and debugging tools (e.g., VCS, Verdi)
Comfortable working in a Linux environment
Strong problem-solving, debugging, and communication skills
Desired Qualifications
Experience developing and debugging UVM-based verification environments and testbenches using SystemVerilog
Understanding of computer architecture and digital design concepts
Knowledge of networking protocols (IP, TCP, UDP)
Experience verifying designs with high-speed interfaces (PCIe, Ethernet, and/or DDR)
Familiarity with C programming and scripting in Python and/or Perl
Compensation
In compliance with Massachusetts law, the anticipated annual base salary range for this position is $90,000 to $216,000. Please note that this range represents the expected base salary for this role at the time of posting. The final offer may vary based on factors such as the candidate's experience, skills, and qualifications. This range does not include other forms of compensation such as potential bonuses, equity, or benefits.
This position requires being on-site at our office in Needham, MA full-time (5 days per week).
HPR does not currently provide employment sponsorship
