FPGA Designer/Verification Engineer

Accedian Networks

• $100K — $120K *
Telecommunications & Hardware
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • Minimum of 5 years experience in FPGA development.
  • Strong VHDL/Verilog skills for synthesizable designs.
  • SystemVerilog knowledge for verification testbench development; UVM experience is advantageous.
  • Solid understanding of FPGA design considerations and timing requirements.
  • Experience with third-party VHDL/Verilog IP integration and validation tools.
  • Familiarity with scripting languages like TCL and Python for automation.
  • Knowledge of Ethernet technologies and ASIC development methodologies is a plus.
  • Excellent communication skills for documentation purposes.
  • Self-motivated with rapid learning ability and proactive problem-solving approach.
  • Bilingual in French and English preferred.

Responsibilities

  • Conduct full FPGA development cycle including architecture, verification strategy, and on-board testing.
  • Write and manage RTL validation test plans, develop verification collateral, and analyze test results.
  • Build and maintain tools/processes for FPGA development efficiency.
  • Engage in project planning and coordination.
  • Translate product requirements into FPGA functional block implementations.
  • Collaborate with multi-disciplinary teams to integrate FPGA with hardware and software designs.

Benefits

  • Confidential handling of applicant information according to EEO guidelines.
Full Job Description
Job Description

This position is for an FPGA Designer/Verification Engineer. It reports to the Manager of FPGA development. We are looking for an FPGA Design/Verification Engineer that can potentially contribute to all phases of FPGA development with specific emphasis on verification. This position requires a strong understanding in FPGA development from concept to an implemented and verified design.

Responsibilities:
  • Full FPGA development cycle involving architecture definition, verification strategy definition, RTL/Testbench coding, simulation, timing analysis, synthesis, place & route and on-board testing.
  • Validate that system meets design requirement: Write test plans for RTL validation. Develop verification collateral (such as BFMs, behavioral checkers, coverage monitors, or score-boards). Define and run system simulation models, and find and implement corrective measures for failing RTL tests. Analyze and use results to modify testing.
  • Build and maintains tools and processes associated with FPGA development.
  • Participate in project planning activities.
  • Understand product requirements, participate in software/FPGA partitioning and implement/validate FPGA functional blocks.
  • Work with other engineers on a team to integrate FPGA designs on projects that include hardware and software design components


Qualifications

  • Minimum of 5 years of pertinent experience.
  • Strong VHDL/Verilog design and coding skills for synthesizable FPGA designs.
  • SystemVerilog and OOP coding skills for verification testbench development. UVM knowledge is an asset.
  • Good understanding of FPGA design considerations including synchronous/asynchronous/CDC timing requirements and FPGA resource utilization.
  • Experience with 3rd-party VHDL/Verilog IP.
  • Experience with scripting languages for tool automation and FPGA validation. TCL and Python knowledge is an asset.
  • Ethernet expertise is an asset. Knowledge of ASIC development methodology is a plus
  • Excellent written and oral communication skills, including the ability to produce clear, concise documentation.
  • Passionate and self-motivated with the ability to learn quickly and independently.
  • Team player capable to interact efficiently within multi-disciplinary engineering team.
  • Pragmatic approach to problem solving.
  • "Can-Do" attitude to overcome any kind of challenges.
  • Ability to take full ownership of his task and project.
  • Bilingual (French and English).


Additional Information

All your information will be kept confidential according to EEO guidelines.

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