Skilled in testbench development and verification planning
Experience with functional coverage analysis and closure
Ability to develop reusable verification components
Familiarity with C/C++ test development and hardware/software integration
Strong troubleshooting skills and ability to work independently
Responsibilities
Develop and maintain SystemVerilog and UVM-based verification testbenches
Create and execute verification plans, test scenarios, and functional tests
Develop reusable verification components and verification IP
Perform functional coverage analysis and drive coverage closure
Develop C-based tests and support hardware/software integration
Debug simulation failures and collaborate with design teams to resolve issues
Support FPGA verification from planning through final sign-off
Benefits
Collaborative work environment with cross-functional teams
Opportunity to work on cutting-edge aerospace and defense projects
Potential for professional growth in a specialized field
Engagement in the full development lifecycle of FPGA verification
Access to advanced tools and technologies in verification engineering
Full Job Description
We are currently hiring for an FPGA Design Verification Engineer for an opportunity based in El Segundo, California. Job Title: FPGA Design Verification Engineer Location: El Segundo, CA Experience: 5+ years Work Authorization: U.S. Citizens only Security Clearance: Secret DoD clearance preferred Job Overview: We are looking for an experienced FPGA Design Verification Engineer with hands-on expertise in SystemVerilog, UVM, and verification testbench development. The ideal candidate will have experience developing verification plans, building reusable verification components, analyzing functional coverage, and supporting FPGA verification activities throughout the development lifecycle. Key Responsibilities:
Develop and maintain SystemVerilog and UVM-based verification testbenches.
Create and execute verification plans, test scenarios, and functional tests.
Develop reusable verification components and verification IP.
Perform functional coverage analysis and drive coverage closure.
Develop C-based tests and support hardware/software integration.
Debug simulation failures and work with design teams to resolve verification issues.
Support FPGA verification from initial planning through final verification sign-off.
Collaborate with hardware, firmware, and system engineering teams.
Required Skills:
At least 5 years of hands-on FPGA design verification experience.
Strong knowledge of SystemVerilog and UVM.
Experience with testbench development and verification planning.
Functional coverage analysis and coverage closure.
