Job Description:
Join the Physical Design team as a Engineer II-Physical Design supporting semiconductor synthesis, floorplanning, placement, clocking, routing, timing, power, physical verification, documentation, and tapeout-readiness activities. This role is best suited for candidates with 2.5–5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, place and route, timing closure, physical verification, or a closely related area.
In this role, you will independently execute defined physical-design assignments and coordinate assigned deliverables, partner with architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, manufacturing, and leadership teams, and help deliver robust performance, power, area, physical-verification closure, reliability, and tapeout readiness.
Responsibilities:
- Develop and maintain defined ASIC or SoC physical-design blocks, constraints, scripts, flows, and design data.
- Translate approved architecture and RTL requirements into synthesis, floorplan, placement, clock, routing, timing, power, and verification objectives.
- Execute implementation, regression, extraction, timing, power, physical-verification, and applicable signoff checks.
- Troubleshoot flow, constraint, timing, congestion, power, signal-integrity, physical-verification, and integration issues.
- Analyze reports, logs, results, defects, risks, dependencies, and technical tradeoffs; recommend actions.
- Maintain design configuration, scripts, run records, waiver evidence, release data, traceability, and technical documentation.
- Coordinate assigned deliverables across architecture, RTL design, verification, DFT, analog, package, methodology, CAD, product, test, and manufacturing teams.
- Support automation, reuse, corrective action, and continuous improvement.
Requirements/Qualifications:
Minimum qualifications: Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field with 2.5–5 years of relevant experience in ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, physical verification, EDA flows, or closely related equivalent experience.
Qualified candidates should demonstrate analytical thinking, semiconductor physical-design judgment, structured problem solving, timing and power analysis, debugging and root-cause analysis, technical documentation, evidence-based communication, cross-functional collaboration, quality focus, and the ability to work with complex architecture, RTL, constraints, libraries, layout, timing, power, physical-verification, reliability, and manufacturing information.
Successful candidates are expected to demonstrate:
- Employment stability, reliability, and sustained accountability in prior roles.
- Effective teamwork and cross-functional collaboration.
- Integrity and accuracy in representing qualifications, experience, and credentials.
Preferred Qualifications:
- Experience with ASIC or SoC physical design, synthesis, floorplanning, placement, clock-tree synthesis, routing, extraction, static timing analysis, power integrity, or physical verification.
- Experience with EDA tools, scripting, automation, design constraints, low-power implementation, variation analysis, design-for-test, advanced process nodes, or tapeout flows.
- Experience resolving timing, congestion, power, signal-integrity, physical-verification, integration, reliability, or manufacturability issues.
- Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, Physics, or a related field.
Travel Time:
0% - 25%
Physical Attributes:
Hearing, Seeing, Talking, Works Alone, Works Around Others
Physical Requirements:
100% inside, 80% sitting, 10% standing, 10% walking
