Job DescriptionBAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification environments. Candidates will be given the opportunity to lead teams, mentor junior engineers, and contribute to the evolution of the company's verification processes and methodologies.
While in this job you will
- Plan, architect, develop, and use configurable, self-checking testbenches implemented in SystemVerilog/UVM and/or VHDL;
- Develop constrained-random, metric-driven test plans and strategies to verify FPGAs performing signal processing and control functions in Electronic Warfare systems;
- Collect and analyze coverage metrics, then use that information to improve the effectiveness of testcases;
- Enhance your leadership skills while leading small to medium sized DV teams
- Create reusable Verification IP to be shared across the organization;
- Drive changes to our process and methodologies.
- Enhance your DV skills as well as your knowledge of Electronic Warfare while working with subject matter experts;
- Mentor junior engineers across multiple U.S. locations
BAE Systems offers competitive pay, benefits, and important work-life balance initiatives including every other Friday Off, Flextime, and Telecommuting. BAE also believes in a culture of recognition for the extraordinary contributions of our skilled employees.
Because of the need for consistent, in-person collaboration and/or the requirement to perform all work onsite due to the nature of this particular role, it will be performed full-time on site.
Current BAE Systems employees are ineligible for sign-on bonuses.
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This position will be posted for at least 5 calendar days. The posting will remain active until the position is filled, or a qualified pool of candidates is identified.
Required Skills and Education- Bachelor's Degree and 8 + years work experience (or equivalent experience)
- Current Security Clearance (Secret), or eligible to obtain one
- Experience planning, architecting, developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL
- Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence)
- Proven track record of managing and executing to schedules, and driving tasks to closure. Candidates should also be comfortable multitasking because they may be asked to support multiple projects.
- Strong communication and documentation skills
- Experience developing and implementing test plans.
- Abilty to work effectively in a multi-site or borderless environment
Preferred Skills and EducationThe following skills/experience are preferred, but not required:
- Perl/Python
- C++/Java
- Git/Jira/BitBucket
- Digital Signal Processing
- Matlab/Simulink
- Working knowledge of VHDL
- FPGA Design Experience
- Experience creating reusable Verification IP.
- Experience leading small to medium teams with accountability for cost, schedule, and quality
- Experience driving process.
- Demonstrated mentoring skills
