Bachelor's or Master's/PhD in Electrical Engineering, Computer Engineering, or related field.
4+ years in ASIC/SoC design verification with experience through tapeout.
Hands-on experience with UVM and SystemVerilog testbench components.
Experience in defining and driving functional coverage closure.
Working knowledge of SystemVerilog Assertions.
Strong debugging skills using waveforms and logs.
Proficiency in Python for automation and regression flows.
Responsibilities
Develop and maintain UVM/SystemVerilog testbenches and tests for verification.
Collaborate with design teams to write verification plans from specifications.
Create SystemVerilog assertions and drive coverage to closure.
Debug simulation failures and work with designers to resolve issues.
Contribute to regression infrastructure and track verification progress.
Support gate-level simulation and sign-off activities.
Benefits
Comprehensive benefits package.
Meaningful equity opportunities.
10% annual bonus potential.
Full Job Description
We are looking for a Design Verification Engineer to join our newly formed verification team and own the functional verification of blocks and subsystems in our SoC, including Efficient's proprietary Fabric technology. You'll work alongside senior DV engineers, RTL designers, and architects to build testbenches, close coverage, and find bugs before silicon does. This is a great opportunity to grow your skills while having a real influence on our products and processes as we move from initial product development to market release and scaled volume production. What You'll Do
Develop and maintain UVM/SystemVerilog testbenches, sequences, and tests for block- and subsystem-level verification.
Write verification plans from design specifications in collaboration with design and architecture teams.
Write SystemVerilog assertions and functional coverage models, and drive coverage to closure.
Debug simulation failures, working with designers to root-cause and fix issues.
Contribute to regression infrastructure, automation, and dashboards that track verification progress.
Support gate-level simulation and other sign-off activities.
Required Qualifications & Experience
Education: Bachelor's or Master's/PhD degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 4+ years of experience in ASIC/SoC design verification, with multiple projects taken through tapeout.
UVM and SystemVerilog: Hands-on experience building and extending UVM testbench components (agents, scoreboards, sequences) and constrained-random tests.
Coverage: Experience defining functional coverage and driving code and functional coverage closure at block or subsystem level.
Assertions: Working knowledge of SystemVerilog Assertions.
Debug Skills: Ability to independently debug simulation failures using waveforms, logs, and design knowledge.
Scripting & Automation: Proficiency in Python for test automation, log analysis, and regression flows.
Communication: Ability to clearly report verification status and issues to the team.
Ways to Stand Out
C/C++ experience for reference models or DPI-based verification.
Exposure to formal verification (JasperGold or similar).
Experience building or using AI agentic flows for DV.
Knowledge of computer architecture or dataflow architectures.
Exposure to power-aware verification (UPF)
We offer a competitive base salary for this role, generally ranging from $130,000 to $180,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
