As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in developing groundbreaking silicon-to-systems solutions - right from technology development and advanced memory designs to product development, systems design and validation resulting in world class memory solutions! In this position, you will collaborate with Micron's various design and verification teams all over the world and support the efforts of groups such as Product Engineering, Test, Probe, Process Integration, Assembly and Marketing to proactively design products that optimize all manufacturing functions and assure the best cost, quality, reliability, time-to-market, and customer satisfaction. You will own physical implementation and top-level integration of large digital designs in our NAND products. Drive blocks and full-chip partitions through synthesis handoff, floorplan, place-and-route, and timing/DRC/LVS closure. Perform hierarchical design planning and top-level assembly. Responsibilities will include, but are not limited to: • Contributing to the development of new product opportunities by assisting with the overall design, layout, and optimization of Memory/Logic/Analog circuits • Parasitic modeling and assisting in design validation, reticle experiments and required tape-out revisions • Leading all aspects of and managing the layout process including floor-planning, placement, and routing • Performing verification processes with modeling and simulation using industry standard simulators • Contributing to cross group communication to work towards standardization and group success • Working with Marketing, Probe, Assembly, Test, Process Integration, and Product Engineering groups to ensure accurate manufacturability of product • Proactively solicit mentorship from Standards, CAD, modeling, and verification groups to improve the design quality • Driving innovation into the future Memory generations within a dynamic work environment Design Planning & Top-Level Integratio • Perform top-level virtual flat placement to explore partitioning options and validate hierarchy quality before commit. • Implement top-level global routing to derive congestion, timing, and pin-feasibility signals that drive planning decisions. • Own partition creation: block shaping, abutment, channel/keep-out definition, and power-domain planning. • Drive pin optimization / pin cutting - pin placement, alignment, and count reduction guided by top-level routing. • Plan and implement repeater / feedthrough insertion: budget top-level nets, place repeaters, and manage crossings across partition boundaries. • Generate block-level constraints (timing budgets, boundary SDC, ILM/ETM models, physical constraints) directly from the design planning tool and hand them off to block owners. • Perform top-level assembly: integrate block-related work (LEF/DEF/GDS/ETM/ILM), close top-level timing, DRC, LVS, and EM/IR, and iterate ECOs to convergence. Block-Level APR • Implement full APR flow (init  floorplan  place  CTS  route  ECO  sign-off) on digital blocks; own block-level STA sign-off across corners alongside DRC, LVS, EM/IR, and antenna closure. • Set up new project and revision environments - collateral (SDC, netlist, LEF, QTM), stdlib migrations, and constraint authoring. • Debug and correlate synthesis vs. APR vs. STA (PPA regressions, DRV, size_only/don't_touch strategy, scan chain stitching). Methodology & Automation • Automate flows in Tcl / SKILL / Python; extend internal make-based flow and contribute to shared analysis tooling and dashboards. • Partner with STA, DFT, CAD, and custom-layout teams; document methodology and provide mentorship to engineers gaining experience. Required Skills & Experience: • 5+ years of digital physical design with at least one full tapeout owned end-to-end. • Bachelor's degree in Computer Engineering or Electrical Engineering • Strong static timing analysis and debug skills. Fluent with PrimeTime across MMMC and OCV/AOCV/POCV; comfortable dissecting violations into clock, data, and derating contributors, and separating real issues from constraint or modeling artifacts. Experience with ILM / ETM block abstractions and ECO fixing. • Hands-on expertise with Cadence Innovus Hierarchical Flow or Synopsys ICC2 Design Planning - virtual flat, partitioning, pin optimization, budgeting, assembly. • Proven experience with top-level digital integration flow end-to-end - driving a full-chip or large-partition design from planning through assembly and hand-off. • Strong flat APR expertise with Innovus (or ICC2): floorplan, place, CTS, route, ECO, sign-off correlation. • Synthesis proficiency with Design Compiler or Genus (WLM + topographical/physical); comfort with size_only, don't_touch, MBFF, scan, clock gating. • Physical verification with Calibre: DRC, LVS, antenna, PERC; hierarchical vs. flat runs and waiver management. • SDC authoring for multi-mode/multi-corner designs; ability to derive and validate block budgets from top-level planning. • Fluent in Tcl and one of Python/Perl for flow automation. • Working proficiency with general-purpose agentic AI applied to engineering work - AI-powered assistants, MCP-based tool integration, and workflow automation. Candidates must be able to use and extend our internal AI toolkit from day one. • Solid grasp of CMOS logic, standard cells, RC extraction, EM/IR, and low-power techniques (MV, power gating, retention). • Linux/Unix, Git or similar VCS, Make-based flows. Preferred / Bonus: • Master's degree or Ph.D. in Computer Engineering or Electrical Engineering • Multi-partition SoC or memory top-level integration; experience driving ECOs across a hierarchy of 5+ blocks. • Clock planning at the top level - clock distribution across partitions, mesh/H-tree hybrids, boundary skew budgeting. Memory (NAND/DRAM) or mixed-signal design experience; comfort working alongside custom-layout and circuit designers. • Familiarity with DFT/scan compression, JTAG, MBIST and their interaction with partitioning. • Familiarity with EDA-vendor AI tools - Cadence Cerebrus / JedAI, Synopsys DSO.ai and copilots, or equivalent. • Contributions to methodology or CAD tooling (published or internal). The US base salary range that Micron Technology estimates it could pay for this full-time position is: $145,000.00 - $246,000.00 a year Additional compensation may include benefits, bonuses and equity. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target base pay for new hire salaries of the position across all US locations. Within the range, individual pay is determined by work location and additional job-related factors, including knowledge, skills, experience, tenure and relevant education or training. The pay scale is subject to change depending on business needs. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.