Deep problem-solving skills for complex verification challenges
Hands-on with SystemVerilog/UVM and building reusable testbenches
Familiarity with IP interfaces like PCIe, Ethernet, and ARM/ARC
Strong collaboration and communication skills across teams
Responsibilities
Own verification for IP subsystems such as PCIe and Ethernet
Manage vendor IP configurations and collaborate with internal teams
Create and maintain UVM/SystemVerilog verification environments
Work with integration and SoC DV teams for seamless IP interactions
Drive verification closure by analyzing gaps and defining metrics
Benefits
Comprehensive medical, dental, and vision insurance
$500/month credit for waiving medical benefits
$2,000/month housing subsidy for nearby residents
Relocation support for new employees in San Jose
Wellness benefits covering fitness and mental health
Free daily lunch and dinner at the office
Full Job Description
Job Summary
We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.
Key responsibilities
End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.
You may be a good fit if you have
5+ years of design verification experience
You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
You collaborate naturally with cross-functional teams - from RTL design to software and emulation - and can clearly communicate technical insights.
Strong candidates may also have experience with
Experience handling vendors and integration of IP/VIP's
UVM/System Verilog
Benefits
Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office
This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.
