BS or MS degree with 12+ years (Lead) or 5+ years (Individual Contributor) in static timing analysis on high-speed designs.
Proficient in industry-standard EDA tools and scripting languages.
Strong understanding of timing and noise analysis checks and constraints.
Excellent communication and collaboration skills.
Preferred: Extensive experience in CPU unit-level timing and noise analysis.
Preferred: Familiarity with timing noise models and hierarchical analysis strategies.
Preferred: Knowledge of physical design flow and methodologies.
Responsibilities
Perform timing and noise analysis on designs and compile results.
Verify the quality of timing/noise runs and check analysis coverage.
Collaborate with design teams to understand violations and suggest fixes.
Generate ECOs based on design requirements.
Develop methodologies and infrastructure for Timing Analysis & Design closure.
Provide feedback to the CAD team on tool/flow issues and enhancement requests.
Benefits
Opportunities for professional development and training.
Collaborative work environment with design teams.
Access to advanced EDA tools and technologies.
Potential for involvement in cutting-edge CPU design projects.
Full Job Description
THE ROLE
As a CPU Static Timing Analysis (STA) Engineer, you will participate in the following :
Responsible for performing timing and noise analysis on designs and rolling up analysis results.
Responsible for verifying the quality of the timing/noise runs and checking analysis coverage.
Responsible for working with the design teams on understanding the violations and providing fixing suggestions/strategies as well as constraint refinements when needed.
Responsible for performing ECO generation per design needs.
Develop essential methodologies and infrastructure for Timing Analysis & Design closure.
Responsible for working with the CAD team and providing feedbacks on tool/flow issues or enhancement requests to improve productivity.
MINIMUM QUALIFICATIONS
Hold a BS or MS degree with 12+ years of experience (for Lead roles) or 5+ years of experience (for Individual Contributor roles) in static timing analysis on high-speed designs.
Knowledge in industry-standard EDA tools and scripting languages.
Understanding various timing and noise analysis checks and corresponding constraints.
Strong communication and collaboration skills.
REQUIREMENTS - PREFERRED
Possess substantial years of experience in CPU unit-level timing and noise analysis
Understanding of timing noise models and hierarchical analysis strategies..
Understanding of advanced technologies and scaling trends.
Knowledge of physical design flow and methodology including logic synthesis, PnR, parasitic extraction, logic equivalence etc., which are related to timing analysis.
Proficient in Python, Perl, or TCL to enhance design productivity and flow efficiency
Experience in using Agentic AI tools for productivity and automation.
