Degree in Electrical/Computer Engineering, Computer Science, or equivalent experience
15+ years of design-verification experience for Principal level, or 4+ years for Senior Engineer
Strong knowledge of interconnect architecture and digital logic protocols
Hands-on experience with functional verification tools and methodologies
Proficiency in C/C++ and/or SystemVerilog, plus a scripting language like Python
Experience in writing and debugging tests for complex digital designs
Responsibilities
Drive verification scope, strategy, and test plans for interconnect fabric
Build and maintain robust verification environments for coherent and non-coherent transactions
Generate directed and random traffic to expose corner cases in design
Partner with architects to correlate RTL against performance models
Define coverage space and analyze metrics for test plan completeness
Collaborate with architecture and RTL teams to root-cause failures and support design fixes
Benefits
Opportunity to work on cutting-edge CPU technology
Collaborative environment with cross-functional teams
Potential for career advancement from Senior to Principal Engineer
Engagement in high-impact projects with significant technical challenges
Access to advanced tools and methodologies in design verification
Full Job Description
Nuvacore is building a ground-up high performance, low-power CPU for next-generation compute workloads. We are seeking Verification Engineers at multiple levels - from Senior Engineer to Principal level - to help prove the correctness of the Nuvacore interconnect fabric. As part of the design verification (DV) team, you will help verify the coherent and non-coherent interconnect - building the test plans, environments, and checkers that find deep bugs in transport, ordering, and coherence long before silicon, working shoulder-to-shoulder with architecture and RTL design. THE ROLE
Plan & Strategy: Drive the verification scope, strategy, and test plans for the interconnect fabric - coherent and non-coherent, including crossbars, routing, and bus interfaces.
Environment Setup: Build, maintain, and scale robust verification environments - stimulus generators, protocol checkers, transactors, and coverage - that exercise coherent and non-coherent transactions end to end.
Test & Debug: Generate directed and random traffic to expose corner cases such as ordering, arbitration, QoS, and deadlock/livelock avoidance.
Performance Verification: Partner with architects to correlate RTL against performance models, hunting bandwidth, latency, and QoS issues.
Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.
REQUIREMENTS - MUST HAVE
Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
Strong knowledge of interconnect/fabric architecture and digital logic - coherent and non-coherent protocols (e.g. AMBA, CHI, TileLink) and on-chip transport.
Hands-on functional verification: test plans, testbenches, protocol checkers, transactors, and coverage.
Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
Experience writing and debugging tests for complex digital designs.
REQUIREMENTS - NICE TO HAVE
Interconnect, network-on-chip (NoC), or fabric verification.
Coherent and non-coherent bus-protocol verification.
Protocol checkers and formal verification (deadlock/livelock, protocol compliance).
Constrained-random verification and coverage-driven closure.
Performance and QoS verification of interconnect.
Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
