5-7 years of experience in compiler optimization or code generation for non-CPU targets
Strong understanding of memory bandwidth and utilization
Ability to design novel compilation approaches from first principles
Proven track record of delivering performance optimizations
Experience with evolving hardware from simulation to deployment
Proficiency in Python, with familiarity in C, C++, or Rust
Responsibilities
Develop code generation passes for hardware execution
Manage scheduling and memory planning for optimal resource utilization
Make fusion and dispatch decisions to enhance computation efficiency
Collaborate on hardware co-design to inform compiler constraints
Validate optimizations through simulation and FPGA testing
Coordinate with frontend engineers on operation generation
Benefits
Flexible work environment
Opportunity to work on cutting-edge hardware technology
Collaborative team culture
Access to advanced simulation and prototyping tools
Potential for professional growth in a rapidly evolving field
Full Job Description
The Role
Normal's hardware runs the most memory-bound parts of large-model inference inside memory itself, rather than shuttling weights to a processor. The software that makes this programmable doesn't exist yet in any standard form. Getting a model correct on that hardware is the frontend's job; making it fast is yours. Our hardware does not look like a CPU or GPU, so its compiler backend can't be borrowed from one. As a Compiler Engineer focused on the backend, you will help design and build the custom compilation that maps LLM inference onto it, from scheduling and memory planning to the code our hardware actually executes.
You will work at the boundary between the compiler and the hardware, closely enough to know when an optimization belongs at a different layer, or when the right answer is a new abstraction. Our chip is pre-silicon, so you will measure your work against our simulators and FPGA prototypes first, and against silicon as it arrives.
What You Will Own
Code Generation: Build the passes that turn lowered programs into the code our hardware executes, designing new compilation approaches where conventional ones don't fit. Success means correct, efficient code for every operation our models need.
Scheduling and Memory Planning: Own how work and data are scheduled and placed across our hardware's resources, measured by utilization and end-to-end latency on LLM inference.
Fusion and Dispatch: Own fusion and dispatch decisions for LLM inference, so the hardware spends its time computing rather than moving data.
Hardware Co-Design: Work the abstraction layer between the compiler and the hardware, and feed compiler constraints back to our hardware architects while the design can still change.
Profiling and Validation: Validate every optimization with measured results from simulators, FPGA prototypes, and then silicon, and maintain a performance regression suite the team trusts.
Cross-Team Handoffs: Take lowered programs from our frontend compiler engineers, and decide with the team which operations the compiler generates and which use hand-tuned kernels.
What Makes You a Great Fit
Deep experience with compiler optimization or code generation for accelerators or other non-CPU targets: scheduling, tiling, fusion, or resource allocation
Comfort working close to hardware: you think in terms of memory bandwidth and utilization as well as asymptotic complexity
Willingness to design compilation approaches from first principles when existing ones don't fit the hardware
Track record of shipping optimizations that moved a measured performance number
Comfort building software for hardware that is still evolving, from simulation through bring-up
Fluency in Python, and familiarity with C, C++, or Rust
Bonus Points
Experience with PyTorch's compilation stack (TorchDynamo, FX, Inductor, torch.export) or other ML compilers, such as IREE, TVM, or XLA
Experience compiling for in-memory, spatial, or other non-von-Neumann compute targets
Background in hardware design tools such as logic synthesis or place-and-route
Experience building or using cycle-level or performance simulators to guide optimization decisions
Contributions to open-source compiler or kernel infrastructure (e.g., PyTorch, Triton, TVM, MLIR, LLVM)
Publishing or presenting compiler or performance work at venues such as MLSys, ASPLOS, or CGO
