Overview of Role The Digital Verification Engineer will work closely with design teams to validate digital circuit implementations, develop test benches, perform functional verification preparing Manufacturing/tester patterns and debug of failing tests. The successful candidate will also contribute to the customization of standard digital verification methodologies and help improve the electronic design automation (EDA) capabilities of the group.
Qualifications:- Master's /PhD degree in electrical/computer engineering
- 5-10 years of industry experience in digital verification
- Experience writing and debugging simulation test benches and tools, as well as proficiency in System Verilog, Universal Verification Module (UVM), assertions, system level verification methodologies and debugging tools.
- Working knowledge of Unix/Linux operating systems, scripting languages, and EDA tools such as Synopsys VCS or Cadence Incisive tools.
- Experience with verification planning, code and functional coverage, assertion-based verification, and formal verification is a plus.
- Skilled in complex problem-solving and critical thinking
- Ability to get your point across effectively, both on-line and in conversation
- Equally comfortable collaborating with a team or driving solo initiatives.
Date: Jun 24, 2026
Country/Region: CA
City: Ottawa
Company: TSMC Technology, Inc.
