MS with 8+ years of relevant experience or PhD with 3+ years in Electrical Engineering, Computer Engineering, Computer Science, or related field
In-depth knowledge of UVM/OVM, semiformal verification, and assertion-based verification
Extensive experience in building verification infrastructure and developing test plans and test cases
Proficient in Verilog, System Verilog, and scripting languages like Python/Perl/TCL/Shell
Familiarity with MIPI, AMBA protocols, and RISC-V/ARM architectures
Experience verifying designs at RTL and post-P&R gate levels
Ability to thrive in a startup environment and provide technical leadership
Responsibilities
Collaborate with design engineers and architects to create detailed test plans for SoC design verification
Build and maintain automation verification infrastructure for SoC architecture and performance
Develop reusable testbenches and test cases for block and system level verification
Create regression strategies and tools, ensuring function coverage and closing verification gaps
Debug and identify root causes of simulation failures alongside design engineers
Support post-silicon validation efforts with test engineers
Mentor junior engineers and drive verification efficiency within the team
Benefits
Flexible work environment
Opportunities for professional development and mentorship
Collaborative team culture
Exposure to cutting-edge technologies in AI/ML and high-speed IO
Potential for career advancement in a growing startup
Full Job Description
Responsibilities:
Collaborate with design engineers and architects to define, document and implement detailed test plans for the SoC design verification
Build and maintain infrastructure/environment for automation verification of SoC architecture, function and performance
Develop reusable testbench, constrained-random/directed test cases, and verification associated behavioral module for both of block levels and system levels
Develop regression strategy, methodology and tools(scripts). Define and measure the function coverage. Close verification holes for design releases and tape-out
Work with design engineers to debug and identify root causes of simulation failure
Support test engineers for post-silicon validation
Mentor and coach team members and junior engineers. Drive verification efficiency
Requirements:
MS with 8+ years of relevant experience or PhD (with 3+ years of experience) in Electrical Engineering, Computer Engineering, Computer Science or related degree
In depth knowledge of UVM/OVM, Semiformal Verification, assertion-based verification as well as hardware and software co-verification methodology
Extensive experience of building verification infrastructure, test planning, coverage closure, testbench and testcases development for function/performance verification
Proficient experience with Verilog, System Verilog, Python/Perl/TCL/Shell scripting, C/C++, System C and industry mainstream ISAs assembly coding
Familiarity with MIPI, AMBA (APB/AHB/AXI) bus protocol, RISC-V/ARM or DSP core
Experience in verifying designs at both of RTL level and post-P&R gate level
Ability to work in a startup environment, and to work both independently and as a team player with the ability to provide technical leadership to other members of the engineering team
Experience in one or more of the following areas considered a strong plus:
Working knowledge of AI/ML Computing, GPU, ISP architectures and accelerators
Experience in verifying mix-signal design and interface of digital and analog
Experience of design verification for highspeed IO such as PCIE and DDR
