Application close date:
02/12/2027
Multiple positions available across our Business Units. You will be matched with an appropriate engineering team based on your skillset and experience and our current business needs.
Timeline: Applications will be reviewed on a rolling basis.
Primary locations: We prioritize placing early career engineers in locations where they can be co-located with their team and the relevant hardware they support. Please indicate in the application where you would be willing to be located.
Responsibilities include but are not limited to: - Contribute to Verilog/SystemVerilog design and verification of digital blocks within larger SoCs
- Support module-level and subsystem-level verification using SystemVerilog/UVM
- Write test plans and functional coverage definitions under guidance from senior team members
- Assist with CDC/RDC/LINT checks and clean-up
- Participate in code coverage and functional coverage closure activities
- Help develop assertions, protocol monitors, and scoreboards for testbenches
- Support integration and verification of external IP (e.g., bus fabrics, standard interfaces)
- Learn and apply industry-standard verification methodologies (UVM, formal verification basics)
- Debug RTL and testbench issues with guidance from senior engineers
- Document design intent, verification results, and test coverage
Qualifications: - BS or MS in Electrical Engineering, Computer Engineering, or related technical field (completed or in final year)
- Coursework or project experience with Verilog/SystemVerilog RTL design or verification
- Understanding of digital logic design fundamentals (combinational/sequential logic, FSMs, timing)
- Familiarity with basic verification concepts (testbenches, simulation, coverage)
- Strong problem-solving skills and attention to detail
- Effective communication and ability to work in a collaborative team environment
Desired: - Academic or internship experience with SystemVerilog/UVM
- Exposure to scripting languages (Python, Perl, Tcl) for automation/tooling
- Coursework or projects involving communications systems, DSP, or FPGA design
- Familiarity with common EDA tools (e.g., VCS, Xcelium, Questa, formal tools)
- Understanding of computer architecture fundamentals (CPUs, bus protocols like AXI)
- Personal projects, capstone work, or research involving digital design/verification (e.g., GitHub repos, senior design projects)
Base Pay Range for:
CA applicants is $129,032.00 - $180,644.10WA applicants is $129,032.00 - $180,644.10
Other site ranges may differCulture StatementDon't meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you're excited about this role but your past experience doesn't align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.
Benefits- Benefits include: Medical, dental, vision, basic and supplemental life insurance, paid parental leave, short and long-term disability, 401(k) with a company match of up to 5%, and an Education Support Program.
- Stock Options for all regular employees (working at least 20 hours/week)
- Paid Time Off: Up to four (4) weeks per year based on weekly scheduled hours, and up to 14 company-paid holidays.
- Dependent on role type and job level, employees may be eligible for benefits and bonuses based on the company's intent to reward individual contributions and enable them to share in the company's results, or other factors at the company's sole discretion. Bonus amounts and eligibility are not guaranteed and subject to change and cancellation. Please check with your recruiter for more details.
