Cisco

ASIC DFT Emulation Technical Lead

Cisco$183K — $263K *
Technical Services
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Bachelor's degree with 8 years of experience, Master's with 6 years, or PhD with 3 years of experience.
  • Experience with emulation platforms like Palladium, Veloce, or Zebu and associated debug methodologies.
  • Proficiency in Verilog and System Verilog.
  • Programming skills in C/C++ and scripting in Tcl or Python/Perl.

Responsibilities

  • Develop advanced emulation environments for multi-terabit system DFT evaluations.
  • Assist in designing, implementing, and debugging test plans during pre-silicon emulation.
  • Collaborate with DFT/ATPG teams to simulate post-silicon patterns.
  • Work with emulation vendors to identify and resolve issues.
  • Demonstrate problem-solving skills and debug with minimal guidance.

Benefits

  • Collaborative and innovative team environment.
  • Opportunity to work on cutting-edge technology in silicon design.
  • Learning and development opportunities to enhance technical skills.
Full Job Description
The application window is expected to close on: 09/29/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Your Impact

As an ASIC DFT - Emulation Technical Lead, you will play a critical role in driving the DFT emulation strategy for Silicon One. You'll architect state-of-the-art emulation environments, lead pre-silicon test plan execution, and validate complex scan, MBIST, and JTAG architectures on platforms like Palladium, Veloce, or Zebu. Partnering closely with front-end RTL, physical design, and ATPG teams, you will troubleshoot critical issues and ensure high-quality post-silicon pattern conversion. Your technical leadership and cross-functional collaboration will guarantee seamless silicon bring-up and optimal test coverage across next-generation hardware platforms.

Key Responsibilities
  • Develop state-of-the-art emulation environments that will be used to evaluate the DFT design of multi-terabit systems.
  • Assist with test plan design, test implementation, and debugging during the pre-silicon emulation process.
  • Work with DFT/ATPG team to simulate the post-silicon patterns.
  • Work with leading emulation vendors to troubleshoot issues.
  • The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.


Minimum Qualifications
  • Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience
  • Prior emulation experience on platforms such as Palladium, Veloce, or Zebu as well as experience with compilation and debug.
  • Prior experience with Verilog and System Verilog.
  • Prior experience with C/C++ and scripting skills with Tcl or Python/Perl.


Preferred Qualifications
  • Prior experience defining DFT Emulation strategy.
  • Prior experience with JTAG protocol, scan architecture, MBIST and boundary scan.
  • UVM and advanced System Verilog knowledge.
  • Post Silicon validation and/or debugging experience.

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