Cisco

ASIC DFT CAD Technical Leader

Cisco$183K — $263K *
Enterprise Technology
8 - 10 years of experience
Job Overview by Ladders

Qualifications

  • 8+ years of experience in DFT, CAD, or test automation for semiconductor designs.
  • Experienced with EDA DFT toolchains like Synopsys TestMAX and Tessent.
  • Proficient in Tcl, Python, Perl, and shell scripting.
  • Skilled in building automated flows in compute farm environments (LSF or similar).
  • Prior experience with SoC integration and cross-functional workflows.
  • Expertise in applying AI/ML techniques to EDA workflows.

Responsibilities

  • Own and drive end-to-end DFT flow architecture.
  • Build and maintain scalable DFT CAD infrastructure from RTL through reporting.
  • Develop robust regression frameworks with orchestration and monitoring.
  • Lead AI-driven automation initiatives for log analysis and regression optimization.
  • Collaborate with various teams to ensure seamless DFT integration.
  • Define and track key metrics, building dashboards for visibility.
  • Standardize flows and enforce best practices across projects.
  • Mentor engineers to drive technical excellence within the team.

Benefits

  • Health, dental, and vision insurance.
  • Retirement savings plan with employer matching.
  • Flexible work hours and remote work options.
  • Professional development opportunities.
  • Generous paid time off and holidays.
Full Job Description
The application window is expected to close on: 07/24/2026
Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Key Responsibilities:
  • Own and drive end-to-end DFT flow architecture.
  • Build and maintain scalable DFT CAD infrastructure from RTL ' DFT insertion, ATPG, simulation, reporting.
  • Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery.
  • Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug.
  • Collaborate with RTL, Physical Design, and Validation teams to ensure seamless DFT integration and signoff.
  • Define and track key metrics (coverage, pattern count, runtime, regression health) and build dashboards for visibility.
  • Standardize flows, improve reusability, and enforce best practices across projects.
  • Evaluate and integrate new tools, methodologies, and AI technologies into existing flows.
  • Mentor and guide engineers, driving technical excellence and innovation within the team.

Minimum Qualifications:
  • 8+ years of experience in DFT, CAD, or test automation for semiconductor designs.
  • Prior experience with EDA DFT toolchain like Synopsys TestMAX, Synopsys VCS, Siemen's Tessent and similar,
  • Experience in Tcl, Python, Perl, and shell scripting.
  • Experience building automated flows and regression systems in compute farm environments (LSF/ or similar)
  • Prior experience with SoC integration and cross-functional workflows.
  • Experience applying AI/ML techniques to EDA workflows (log analysis, anomaly detection, predictive insights).

Preferred Qualifications:
  • Familiarity with data analytics tools (Python/pandas, dashboards, visualization tools).
  • Experience with large-scale regression systems and distributed job management.
  • Exposure to ATE/tester formats (e.g., STIL) and silicon bring-up/debug.

About Cisco

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Size
79,500 employees
Market Cap
$194.5 billion
Industry
Net Income
$10.1 billion
Founded
2014
5 Year Trend
+1.4%
Revenue
$48 billion
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