Job Area:Engineering Group, Engineering Group > ASICS Engineering
General Summary:Our mission is to deliver industry-leading System-on-Chip (SoC) solutions that power smartphones, PCs, XR devices, automotive platforms, and emerging technologies. We are seeking talented ASIC Design Engineers to contribute to the architecture, microarchitecture, design, and deployment of next-generation SoC Interconnects, Cache and Memory Subsystems, and High-Speed DDR Memory Controllers.
In this role, you will work closely with architecture, verification, physical design, and software teams to develop high-performance, power-efficient silicon solutions that enable Qualcomm's most advanced products.
Responsibilities- Develop microarchitecture definitions and design specifications for complex SoC subsystems.
- Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components.
- Collaborate with system architects to evaluate hardware feasibility of new features, algorithms, and performance requirements.
- Optimize designs for performance, power, area, timing, and scalability.
- Work closely with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals.
- Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
- Participate in system-level integration and debugging throughout the product development cycle.
- Investigate and resolve pre-silicon and post-silicon issues.
- Contribute to C/C++ modeling, design methodologies, and process improvements that enhance engineering productivity and design quality.
- Collaborate across cross-functional teams to successfully deliver silicon for production.
Required Qualifications- Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 0-4+ years of industry experience or relevant academic experience in ASIC/SoC design.
- Experience or coursework in: Verilog and/or SystemVerilog RTL design Computer Architecture ASIC design methodologies Digital logic design C, C++, and/or Python programming
- Strong analytical and problem-solving skills.
- Excellent communication and collaboration skills.
Preferred QualificationsExperience or knowledge in one or more of the following areas:
- SoC interconnects and on-chip communication fabrics
- Cache and memory subsystem design
- DDR/LPDDR memory controller architecture and design
- ARM or x86 processor architectures and bus protocols
- RTL development for CPUs, cache controllers, or memory controllers
- Low-power design methodologies
- Functional verification and coverage-driven verification techniques
- Synopsys synthesis tools and ASIC implementation flows
- Timing closure, physical design support, and power optimization
- Silicon bring-up and post-silicon debug
Minimum Qualifications:• Bachelor's degree in Science, Engineering, or related field.
Pay range and Other Compensation & Benefits: $101,400.00 - $152,200.00
The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.
