Analog IC Design Engineer

Talentlab

$90K — $130K *
Consumer Technology
5 - 7 years of experience
Job Overview by Ladders

Qualifications

  • MSc or PhD in Electrical Engineering or related field.
  • 5+ years of analog IC design experience with silicon-proven results.
  • Hands-on experience with advanced CMOS nodes.
  • Design experience with high-performance blocks such as CTLE, ADCs, VCOs, and others.
  • Strong understanding of parasitic-aware layout and reliability principles.
  • Proficient in EDA tools for design workflows.
  • Solid background in simulation, including SPICE and Verilog-A.

Responsibilities

  • Design and verify high-performance analog blocks according to specifications.
  • Collaborate effectively with a team of elite engineers.
  • Optimize circuit designs to achieve power, performance, and area goals.
  • Propose and implement strategies for design and verification.
  • Review and guide physical layout to minimize parasitics and variability.
  • Present simulation outcomes for peer review and validation.
  • Document design features and performance metrics.
  • Support post-silicon validation and performance correlation.

Benefits

  • Collaborative work environment with elite engineers.
  • Contribution to cutting-edge circuit design in advanced technologies.
  • Opportunity to optimize circuits for performance and efficiency.
  • Engagement in a supportive team with shared ownership of projects.
Full Job Description
Analog IC Design Engineer

As an Analog IC Design Engineer, you'll contribute to cutting-edge analog and mixed-signal circuit design from concept through silicon characterization, collaborating with an elite team to push performance and power boundaries across advanced CMOS nodes.

What You'll Do
  • Design and verify high-performance analog blocks aligned with system and industry specifications.
  • Collaborate with a team of top-tier engineers-supporting and being supported through shared ownership and technical leadership.
  • Optimize circuits to meet power, performance, and area (PPA) goals.
  • Propose and implement design and verification strategies to ensure robust, silicon-proven circuits.
  • Guide and review physical layout to reduce parasitics, stress, and process variability.
  • Present simulation results for peer review and technical validation.
  • Document design features, testbench setups, and key performance indicators.
  • Support the characterization team to validate post-silicon performance and correlate measurements to simulations.

What You'll Need
  • MSc or PhD in Electrical Engineering, Engineering Science, or a related technical field.
  • 5+ years of experience in analog IC design, preferably with silicon-proven results.
  • Hands-on experience with advanced CMOS nodes.
  • Design experience with any of the following blocks: CTLE, slicers, high-speed ADCs, VCOs, PIs, PLLs, bandgaps, regulators, serializers/deserializers, phase detectors, or high-speed TX/RX architectures.
  • Strong understanding of parasitic-aware layout and reliability considerations (aging, stress, EM).
  • Proficiency with EDA tools for schematic, layout, and verification workflows.
  • Solid simulation background, including SPICE and behavioral modeling using Verilog-A.

Location: Toronto - reporting to the Senior Director, Connectivity Products Group.
Please reach out to [redacted] with your resume if you're a fit for the position and interested in learning more.

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