Deep understanding of AI chip design processes (GPUs, TPUs, XPUs, custom ASICs)
Experience with memory sub-systems in multi-die systems
Knowledge of LLM inference workloads and their hardware implications
Experience with multi-die designs is strongly preferred
Familiarity with MCM and chiplet architectures
Proven ability to partition workloads across multiple chips and packages
Responsibilities
Own the logical architecture for A-0 and A-1 wafer products
Collaborate with XPU/Compute chip architect and memory architect
Synthesize final wafer-level architecture
Ensure optimal performance of memory sub-systems
Analyze and address implications of LLM workloads on hardware
Benefits
Collaborative work environment with leading experts
Opportunity to influence cutting-edge AI chip designs
Access to advanced technology and resources
Professional development and growth opportunities
Full Job Description
What We're Looking For:
We're looking for an architect to own the logical architecture for the A-0 and A-1 wafer products. You will work with the XPU/Compute chip architect and the memory architect to synthesize the final wafer-level architecture.
Ideal Background:
An ideal candidate will have:
Deep understanding and hands-on experience in the design process of AI chips, such as GPUs, TPUs, XPUs, custom ASICs, etc
Understanding of memory sub-systems and interactions in multi-die systems
Understanding of LLM inference workloads, especially at a software level and its implications for hardware (system, package, network, die-level) systems
Strongly Preferred:
Experience with multi-die designs
Experience with MCM and chiplet based architectures and architectural partitioning across them
Experience in partitioning workloads across multiple chips and chip packages
