Job Details:Job Description: The Technology Development (TD) Quality and Reliability organization enables successful deployment of Intel's leading-edge process technologies through silicon-based quality, reliability, and technology readiness assessments.
The Memory Quality and Reliability team partners with Design, Device Engineering, Product Development Engineering, and Yield organizations to develop, characterize and certify SRAM, Register File (RF), and Fuse array for advanced technology nodes. The team supports technology certification and PDK release milestones by establishing certification strategies, developing certification methodologies, performing silicon characterization, generating predictive Vccmin models, and assessing product risk for internal and external customers.
Role Overview
We are seeking an experienced Memory Quality and Reliability Engineer to drive post-silicon memory characterization, certification, and technology readiness activities for advanced SRAM, Register File (RF) and/or fuse array.
In this role, you will help improving certification methodologies, analyzing large-scale silicon characterization data, developing Vccmin/Vmax predictive models, assessing silicon-to-simulation correlation (Sil2Sim), and providing risk assessments that guide technology development, product deployment, and PDK release decisions. You will work with design, device, process, test, and yield organizations to transform silicon learning into certification decisions and actionable technology improvements.
Key Responsibilities
0Plan and execute SRAM, RF, and/or Fuse technology certification supporting technology development and certification milestones.
0Define and maintain certification methodologies and criteria, test strategies, and readiness requirements for memory array.
0Drive memory array characterization across multiple operating conditions to evaluate Vmin, Vmax, aging behavior, variability, and design margins.
0Analyze silicon characterization data to identify performance gaps, failure signatures, systematic trends, and technology risks.
0Develop, validate, and maintain silicon-based Vccmin and Vmax predictive models used for technology certification, PDK releases, and product guidance.
0Perform silicon-to-simulation (Sil2Sim) correlation assessments and drive understanding of discrepancies between measured silicon behavior and design predictions.
0Collaborate with Yield, Design, Device Engineering, PDE, Defect Rel and FIFA teams to define root-cause hypotheses, resolution paths, and technology improvement recommendations on meeting technology commit for memory offers.
0Generate certification reports, readiness assessments, and risk projections that support technology deployment decisions.
0Present technical findings and recommendations to engineering leadership, program teams, and customers.
0Drive continuous improvement of memory certification methodologies, modeling approaches, characterization flows, and data analytics infrastructure.
0Provide technical mentorship and leadership within a highly collaborative cross-functional environment.
Behavioral Traits
0Demonstrated ability to influence across organizational boundaries and drive resolution of complex technical challenges.
0Strong analytical and problem-solving skills with a data-driven decision-making approach.
0Ability to work effectively in ambiguous, fast-paced technology development environments.
0Excellent written and verbal communication skills, including presentation of complex technical topics to diverse stakeholders.
0Self-motivated and capable of independently driving technical programs from problem definition through closure.
Qualifications:Qualifications
Minimum Qualifications
0Ph.D. in Electrical Engineering, Computer Engineering, Physics or related discipline with 2+ years of semiconductor industry experience OR M.S. in Electrical Engineering, Computer Engineering, Physics, Materials Science, or related discipline with 6+ years of semiconductor industry experience.
02+ years of hands-on experience with memory testing.
02+ years of experience performing quantitative analysis of large-scale memory or semiconductor datasets using statistical methods such as DOE, SPC, regression analysis, hypothesis testing, or multivariate analysis.
02+ years of hands-on experience using JMP and Python for data analysis, statistical modeling, process optimization, automation, or data visualization.
Preferred Qualifications
0Experience in memory design, characterization, validation, modeling, product development, quality, reliability, or technology development.
0Strong understanding of SRAM and/or Register File design fundamentals, silicon characterization techniques, and variability analysis.
0Experience developing silicon-based predictive models, statistical distributions, guardbands, and product risk projections.
0Knowledge of Vmin/Vmax characterization methodologies, memory margin assessment, array screening techniques, or design technology co-optimization.
0Experience with silicon-to-simulation correlation (Sil2Sim), SPICE modeling, or design validation.
0Familiarity with technology certification, PDK development, or product deployment processes.
0Programming experience in Python, JSL, SQL, or data analytics frameworks.
Job Type:Experienced Hire
Shift:Shift 1 (United States of America)
Primary Location:US, California, Folsom
Additional Locations:US, California, Santa Clara, US, Oregon, Hillsboro
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $155,520.00-219,550.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.
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