System Architect Verification Engineer
Ottawa, ON, Canada | Full-Time | Ranovus
ABOUT THE ROLE
The System Verification Engineer develops and runs behavioral simulations and control verification tests for the Ranovus Odin optical engine. Working in System Verilog and RTL, you will validate control state machines, bring-up sequences, and link training algorithms before silicon is available -- ensuring firmware and ASIC logic are correct before the first chip arrives. This role works closely with the existing verification lead and is an opportunity to grow into a senior position.
KEY RESPONSIBILITIES
- Develop and maintain System Verilog behavioral models of PIC, ASIC, and Laser subsystems for pre-silicon system simulation.
- Build and run control verification testbenches: bring-up sequences, link training, OE calibration, and fault recovery state machines.
- Perform RTL-level verification of ASIC control blocks in collaboration with the ASIC team.
- Develop and maintain regression environments for control algorithm and bring-up validation.
- Run corner case simulations across PVT (process, voltage, temperature) conditions and aging scenarios.
- Correlate simulation results against lab measurements to validate model accuracy.
- Support pre-silicon firmware validation in collaboration with the FW team.
- Extend the system simulation environment as new blocks and features are added.
REQUIRED QUALIFICATIONS
- B.S. or M.S. in Electrical Engineering or related field.
- 4+ years in digital or mixed-signal verification using System Verilog.
- Familiarity with RTL simulation tools (VCS, Xcelium, or ModelSim).
- Understanding of control state machines and hardware bring-up sequencing.
- Python or MATLAB for scripting, data analysis, and regression automation.
NICE TO HAVE
- Experience with Verilog-A or Verilog-AMS for modeling analog or optical components.
- Experience with optical or photonic system simulation.
- UVM (Universal Verification Methodology) background.
- Familiarity with SPICE or mixed-signal analog simulation.
- Understanding of PAM4 link behavior and BER analysis.
- Exposure to SerDes or high-speed interface IP verification.
