Develops and prepares multi-dimensional layouts and detailed drawings of the semiconductor devices from schematics and related geometry provided by design engineering. Work may be completed through use of CAD or other computerized equipment. Checks dimensions, writes specifications, and verifies completed drawings, artwork or digitized plots. May check design layouts and detailed drawings. Position overview: As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will provide detailed drawings of semiconductor devices from schematics and related geometry provided by design engineers, verify data integrity, and take the lead in major block developments. You'll be expected to communicate effectively with other functional groups across global sites, e.g. TD, design, verification, and CAD. We're seeking a self-starter who can learn rapidly and adapt quickly to changing priorities. Responsibilities: • Organize and prioritize logistics and resource allocations to meet scheduled deadlines and proactively develop methodologies for issue resolution • Contribute to group management and technical innovation • Assign resources, schedule tasks, provide direction, and deliver quality-controlled results • Contribute to projects in a globally distributed design/layout environment • Effectively mentor junior team members • Contribute to the improvement of layout efficiency through the development of automation and new methodologies; Lead, plan, and deliver major blocks and product revisions. Minimum qualifications: • AS or Bachelor's in Electronics, Electrical Engineering, or a related field plus 10 years of direct experience in semiconductor layout design • Deep working knowledge of EDA tools (i.e. Cadence Virtuoso, Synopsys, Calibre) • Demonstrate a strong ability to debug problems through root-cause analysis, find effective and efficient solutions, and collaborate with the engineering staff • Skilled in developing and applying custom layout, floor-planning, signal-planning and power-planning methodologies • Strong verbal and written communication skills • In-depth understanding of design rules and delivering quality layouts • Strong physical verification analysis and debugging skills Preferred qualifications: • 10+ years direct experience in semiconductor layout design • BS degree in a related field • Project leadership in quality optimization, die size shrinkage • IC layout design experience with NAND, DRAM and/or SRAM • Programming skills and Leveraging Artificial Intelligence (AI) to layout workflow