Advanced Micro Devices, Inc

Sr. Systems Design Engineer - Data Center GPU

Advanced Micro Devices, Inc$110K — $130K *
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • 5-7 years of experience in post-silicon validation or semiconductor engineering
  • Proficient in programming/scripting languages like C/C++, Python, or Perl
  • Strong understanding of SoC architecture and multi-die designs
  • Knowledge of hardware debugging techniques and methodologies
  • Familiarity with memory and I/O subsystem architectures
  • Ability to analyze complex systems and identify root causes of failures
  • Self-motivated with a strong attention to detail and problem-solving skills.

Responsibilities

  • Execute post-silicon validation efforts for SOC-level IP blocks
  • Debug hardware and system-level issues during SOC programs
  • Perform post-silicon debug analysis using various tools
  • Triaging failures across multiple IP domains with senior guidance
  • Collaborate with teams to validate and optimize features on time
  • Develop and maintain validation tests for error handling scenarios
  • Engage in modeling and debug frameworks to root-cause silicon failures.

Benefits

  • Comprehensive health and wellness plans
  • Flexible work arrangements, including hybrid options
  • Opportunities for continuous career development
  • Supportive environment for technical innovation
  • Access to cutting-edge technology and resources.
Full Job Description
THE ROLE:

We are looking for a dynamic, energetic Sr. Systems Design Engineer to join our growing Data Center GPU team. As a key contributor to the success of AMD's product, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market. The Systems Design Engineering team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.

THE PERSON:

In this role, you will drive balanced, scalable, and automated solutions. In this high visibility position, your software systems engineering expertise will be necessary towards Product development, definition, and root cause resolution.

KEY RESPONSIBILITIES:
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Executing and contributing to post-silicon validation efforts for SOC-level IP blocks, including test plan development, test execution, coverage tracking, and issue reporting across program milestones
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Debugging hardware and system-level issues found during bring-up, validation, and production phases of SOC programs, with a focus on system IP blocks such as DMA engines, interrupt controllers, and data path logic
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Performing post-silicon debug analysis using scan dump tools and debug reports to investigate hangs, stalls, and error conditions at the IP and system level
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Triaging failures by collecting and correlating debug data across multiple IP domains, with guidance from senior engineers on complex cross-chiplet issues
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Working with multiple teams and tracking test execution to make sure all features are validated and optimized on time
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Working closely with design, firmware, driver, software runtime, and kernel teams to understand IP behavior, error propagation, software-hardware interactions, and power management dependencies
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Developing and maintaining validation test content targeting error handling, fault injection, and power management scenarios
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Engaging in hardware/software modeling and debug frameworks to reproduce and root-cause silicon failures
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Participating in collaborative triage and debug efforts across multiple teams and IP domains, progressively taking ownership of specific IP areas

PREFERRED EXPERIENCE:
  • Experience in post-silicon validation, hardware debug, or a related semiconductor engineering role
  • Programming/scripting skills (e.g., C/C++, Python, Perl)
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Debug techniques and methodologies for post-silicon validation
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Experience with board/platform-level debugging, including bring-up, sequencing, analysis, and optimization
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Knowledge of SoC system architecture, including multi-die or chiplet-based designs
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Understanding of cache hierarchies, buffer allocation and management, ring buffers, FIFO structures, credit-based flow control, and tag tracking mechanisms
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Familiarity with DMA, interrupt handling, memory subsystem, or I/O subsystem architectures
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Knowledge of memory management concepts including address translation, virtual memory, TLB operation, and page fault handling
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Familiarity with software runtime environments, kernel-level drivers, or OS-level interfaces that interact with hardware IPs
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Exposure to RAS concepts - error detection, poison propagation, machine check logging, and watchdog mechanisms
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Experience with scan dump analysis or JTAG-based post-silicon debug tools
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Strong analytical/problem-solving skills and pronounced attention to detail
  • p]:inline" style="font-family: arial, helvetica, sans-serif; font-size: 12pt;" data-streamdown="list-item">Must be a self-starter, able to independently drive tasks to completion and willing to ramp up on new IP domains through documentation and hands-on debug


ACADEMIC CREDENTIALS:

Bachelors or Masters degree in electrical or computer engineering

LOCATION:

Markham, ON

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Benefits offered are described: AMD benefits at a glance.

This posting is for an existing vacancy.

About Advanced Micro Devices, Inc

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Learn more about Advanced Micro Devices, Inc
Size
15,500 employees
Market Cap
$100.9 billion
Industry
Net Income
$2.4 billion
Founded
1969
5 Year Trend
+30.9%
Revenue
$9.7 billion
NASDAQ

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