Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant experience in synthesis and STA for ASICs or large FPGAs
Strong hands-on experience with industry tools (e.g., Design Compiler, PrimeTime)
Proven production-quality SDC and ECO methodology
Solid RTL literacy (SystemVerilog/Verilog)
Ability to translate performance requirements into implementable constraints
Responsibilities
Own synthesis flows and SDC for DSP data paths and high-speed interfaces
Run and sign off STA; analyze critical paths and margin
Drive timing and functional ECO loops with RTL and physical design
Partner with DSP/RTL on architecture trade-offs
Support lint, CDC, and synthesis-clean RTL
Support FPGA and ASIC lab bring-up when timing or constraints are implicated
Contribute to technical strategy, design reviews, and mentoring
Benefits
Opportunity to shape system capability and product differentiation
Work on cutting-edge phased-array ASIC and FPGA solutions
Collaborative environment with early senior digital hires
Involvement in technical strategy and design reviews
Potential for career growth and mentoring opportunities
Full Job Description
The Role
We're looking for a Senior Synthesis / Timing Engineer who can own constraints, logical synthesis, and static timing from RTL through sign-off for our phased-array ASIC and FPGA solutions. As one of our early senior digital hires, you will make the beamforming and adaptive data paths meet throughput, latency, and power-bridging algorithm RTL to a timing-clean netlist that PD can close.
You'll work end-to-end: SDC and multi-mode constraints, synthesis, STA, ECO loops, lint/CDC/formal handoff, and support for place-and-route and lab validation. The decisions you make will directly shape system capability and product differentiation.
Responsibilities
Own synthesis flows and SDC for DSP data paths, beamforming engines, control logic, and high-speed interfaces (multi-clock, multi-mode, including DFT/test modes)
Run and sign off STA (including OCV/AOCV as applicable); analyze critical paths, SI, and margin
Drive timing and functional ECO loops with RTL and physical design; verify with formal (LEC) and STA
Partner with DSP/RTL on architecture trade-offs (throughput, latency, area, power) and with DFT on scan/test clocks
Support lint, CDC, and synthesis-clean RTL; feed PD with constraints, floorplan guidance, and timing budgets
Support FPGA and ASIC lab bring-up when timing or constraints are implicated
Contribute to technical strategy, design reviews, documentation, and mentoring as the team grows
Minimum Qualifications
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
7-10 years of relevant experience in synthesis and STA for ASICs or large FPGAs
Strong hands-on experience with industry tools (e.g., Design Compiler / Fusion Compiler / Genus, PrimeTime or Tempus)
Proven production-quality SDC, multi-mode multi-corner timing closure, and ECO methodology
Solid RTL literacy (SystemVerilog/Verilog) and ability to work with DSP-heavy, high-utilization designs
Demonstrated ability to translate performance requirements into implementable constraints and closed timing
Preferred Qualifications
MSc or PhD with focus on VLSI, communications, or radar systems
Experience taking designs from RTL through synthesis, timing closure, and post-silicon or FPGA validation
Background in communications (5G/6G, satellite) or radar phased arrays
Familiarity with high-speed interfaces, AXI/APB, low-power techniques, UPF, and Cadence/Synopsys PD tools
Prior work on phased-array or multi-antenna systems from concept through fielded product
This position requires access to information controlled under ITAR/EAR; applicants must be U.S. persons as defined in 22 CFR 120.62.
