Role OverviewAs Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) - ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.
What You Will Do- Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
- Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
- Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
- Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
- Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs
- Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups
- Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production
What You Will Bring- BS in Electrical/Electronic Engineering or equivalent practical experience
- 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
- Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
- Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
- Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
- Proven track record routing 112G SerDes and complex DDR5/HBM interfaces
Preferred Qualifications- Experience establishing a Library Management System and standardized footprint/padstack creation processes
- Familiarity with PLM/PDM integration for managing layout releases and ECO workflows
- Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs
