SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES: - Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS: - Ability to work extended hours and weekends as needed to meet critical project milestones
ITAR REQUIREMENTS:- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. a7 1157, or (iv) Asylee under 8 U.S.C. a7 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
