Bachelor's, Master's, or Ph.D. in Computer/Electrical Engineering
5+ years of experience in performance modeling and simulation using SystemC
Strong background in computer/graphics architecture, ML, and LLMs
Hands-on experience with SystemC/TLM simulation, modeling, and performance analysis
Responsibilities
Build SystemC performance models for AI storage solutions covering various components
Improve AI/ML ASIC architecture performance through hardware/software co-optimization
Conduct workload analysis of ASICs and AI/datacenter solutions to identify performance opportunities
Collaborate with architecture teams to optimize datacenter technologies
Model and optimize components of AI/ML accelerator ASICs
Perform performance modeling for large-scale LLM training/inference across modalities
Architect memory-efficient training systems using cutting-edge optimization techniques
Benefits
Flexible work arrangements
Collaborative and innovative work environment
Access to cutting-edge technology and research
Professional development opportunities
Health and wellness programs
Full Job Description
Job Summary
In this AI/ML HBF ASIC Performance Modeling position, you will develop high-performance simulation models and modeling methodologies for Sandisk's next-generation High Bandwidth Flash (HBF) AI Storage Solutions. You will work at the intersection of ASIC architecture, AI/ML workloads, memory systems, and system-level performance engineering to evaluate architectural choices before silicon implementation. You will develop and enhance SystemC/TLM-based performance models representing key HBF ASIC components and their interactions with GPU/TPU/xPU accelerators. The role requires strong SystemC/C++ development skills combined with a solid understanding of computer architecture and performance analysis.
Key Responsibilities
Develop, maintain, and enhance SystemC/TLM 2.0 transaction-level performance models for HBF ASICs and AI Storage Solutions, enabling rapid architectural exploration before RTL implementation
Model critical ASIC subsystems including UCIe/PCIe/CXL interfaces, NoC, DMA engines, queues and buffers, memory controllers, embedded processors, NAND interfaces, and high-bandwidth datapaths
Develop configurable modeling infrastructure allowing architects to perform architectural what-if analysis, parameter sweeps, bottleneck identification, and design-space exploration
Characterize AI/ML and LLM workloads, including training and inference workloads, Dense and Mixture-of-Experts models, attention/KV-cache traffic, and accelerator-to-storage data movement
Analyze end-to-end performance between GPU/TPU/xPU accelerators and HBF, identifying opportunities to improve effective bandwidth, latency, concurrency, and hardware utilization
Partner with ASIC architects to evaluate alternative microarchitectures and quantitatively influence architecture specifications and product decisions
Develop performance metrics, statistics, traces, visualization, regression, and analysis methodologies that enable rapid identification and root-cause analysis of performance bottlenecks
Correlate SystemC model behavior against RTL simulation, emulation, FPGA prototypes, and silicon measurements where available, improving model fidelity throughout the product lifecycle and Model-to-RTL/hardware validation.
Required Qualifications
Bachelors/Masters/Phd degree with 5+ years of relevant experience in Computer Engineering, Electrical Engineering, or Computer Science
Strong hands-on expertise developing simulation and performance models using SystemC, TLM 2.0, C/C++, and object-oriented software design
Strong understanding of computer architecture, including NoC/interconnects, memory hierarchy, queues, arbitration, DMA, caching, memory controllers, and high-bandwidth I/O
Accurately model architecture-level timing, concurrency, bandwidth, latency, contention, backpressure, arbitration, resource utilization, and pipeline behavior
Experience analyzing system performance including throughput, latency, contention, utilization, queue occupancy, backpressure, and bottleneck identification
Experience developing performance models for AI/ML accelerators, GPUs/TPUs/NPUs, datacenter ASICs, storage controllers, or memory systems
Knowledge of LLM training and inference, including attention, KV cache, Mixture-of-Experts, batching, and memory-bandwidth requirements
Experience with SystemC/TLM model integration, RTL/TLM co-simulation, model correlation, regression infrastructure, and architectural design-space exploration.
