Role description
SoC Design Verification Engineer
The Role
UST is searching for two experienced SoC Design Verification Engineers to own functional and performance verification for complex System-on-Chip designs. You will build and maintain UVM-based verification environments, and develop test benches, test cases, and coverage models that take a design from core-level verification through full SoC integration. You will work closely with design and architecture teams to clarify specifications, surface verification risks early, and protect the quality and reliability of our products. Success in this role means closing coverage against the verification plan and catching design defects before silicon is committed.
What You'll Do
• Develop and execute verification plans for complex SoC designs, covering functional and performance verification at the core and SoC levels.
• Perform functional and performance verification using simulation, emulation, and formal verification techniques.
• Create and maintain UVM-based verification environments, test benches, test cases, and coverage models in SystemVerilog and C++.
• Run regressions in Synopsys VCS or Cadence Xcelium, and debug and analyze simulation results to isolate and resolve design issues.
• Review design specifications and architecture with design teams to identify verification challenges early in the development cycle.
• Develop Python and C/C++ scripts to automate verification flows and results analysis.
• Document verification results, track coverage and progress, and participate in code reviews to improve verification methodologies.
This position description identifies the responsibilities and tasks typically associated with the performance of the position. Other relevant essential functions may be required.
What You Need
Required
• 3-5 years of SoC verification experience, including SoC-level functional and performance verification
• Bachelor's or master's degree in electrical engineering, computer engineering, or a related field
• Strong understanding of digital design principles and SoC architecture
• Proficiency in SystemVerilog and UVM for building verification environments
• Proficiency in Python and C/C++ for scripting and test development
• Hands-on experience with simulation tools such as Synopsys VCS or Cadence Xcelium, including debugging simulation results
Preferred
• Proficiency in Verilog or VHDL
• Experience with formal verification techniques
• Experience with emulation platforms
• Experience with OVM or VMM verification methodologies
• Working knowledge of industry-standard protocols such as AXI, AHB, PCIe, and DDR
Location & Compensation
Compensation can differ depending on factors including but not limited to the specific office location, role, skill set, education, and level of experience. UST provides a reasonable range of compensation for roles that may be hired in various U.S. markets as set forth below.
Role Location: Mountain View, CA
Compensation Range: $101,000 - $152,000
Benefits
Full-time, regular employees accrue a minimum of 10 days of paid vacation per year, receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year), 10 paid holidays, and are eligible for paid bereavement leave and jury duty. They are eligible to participate in the Company's 401(k) Retirement Plan with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance, as well as the following Company-paid Employee Only benefits: basic life insurance, accidental death and disability insurance, and short- and long-term disability benefits. Regular employees may purchase additional voluntary short-term disability benefits, and participate in a Health Savings Account (HSA) as well as a Flexible Spending Account (FSA) for healthcare, dependent child care, and/or commuting expenses as allowable under IRS guidelines. Benefits offerings vary in Puerto Rico.
Part-time employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) Retirement Plan with employer matching.
Full-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year) and are eligible to participate in the Company's 401(k) program with employer matching. They and their dependents residing in the US are eligible for medical, dental, and vision insurance.
Part-time temporary employees receive 6 days of paid sick leave each year (pro-rated for new hires throughout the year).
All US employees who work in a state or locality with more generous paid sick leave benefits than specified here will receive the benefit of those sick leave laws.
As part of our recruitment process, UST may use AI or automated tools to support activities such as application screening, scheduling, or interview assistance. All hiring decisions are made by our recruitment team. Where applicable law requires it, further notice will be provided separately.
