5-7 years of experience in SoC architecture and design
Proven track record of owning specs and driving implementation for at least one SoC/die
Deep understanding of architecture, microarchitecture, and physical design processes
Ability to coordinate with cross-functional teams for SoC implementation
Familiarity with SoC interactions with packages, memory subsystems, and I/O
Responsibilities
Own the detailed SoC-level architecture for A-0 and A-1 wafer-scale systems
Collaborate with architecture and ASIC design teams to create implementable specifications
Drive the execution of SoC implementations
Coordinate with teams responsible for interacting blocks within the SoC
Ensure alignment between architecture and physical design requirements
Benefits
Opportunity to work on cutting-edge wafer-scale systems
Collaborative environment with cross-functional teams
Potential for professional growth in a rapidly evolving field
Engagement in high-impact projects with significant technological advancements
Access to resources for continuous learning and development
Full Job Description
What We're Looking For:
We're looking for SoC architects to own the detailed SoC-level architecture of dies on the A-0 and A-1 wafer-scale systems. You will work with the architecture and ASIC design teams to create implementable specs and drive the execution of said implementations.
Ideal Background:
An ideal candidate will have:
Experience with full ownership of the specs and drove implementation for at least one SoC/die
A deep understanding of the process of architecture, microarchitecture and physical design and the ability to coordinate with various groups to drive implementation of SoCs
Understanding of SoC interactions with packages, memory subsystems and IO, and ability to work with teams who are responsible for said interacting blocks
Nice to Have:
Experience with multi-die/multi-chiplet/MCM designs
Experience with reticle-max/large-die SoC architecture
Understanding of levers available for improving PPA
Track record of very high speed A0 silicon delivery
