Silicon Packaging Engineer

Silicon Packaging Engineer Responsibilities Perform package design for AI/ML and networking applications custom Si with single-chip/multi-chip and SiP/module packaging, design feasibility studies and analyses to ensure good manufacturing at ODM • Lead development of next-generation advanced packaging technologies from concept to product, including test vehicle definition and building with ecosystem partners • Work with internal Si, architecture and system teams, and externally with engaged partners, ODM, design houses and OSAT companies • Perform design analysis and what-if scenarios for novel packaging schemes such as 2.5D/3D and heterogeneous integration to improve package form factor for next-generation versions of current products • Influence ASIC vendors, foundry, ODM and OSAT partners' roadmaps and align with Meta ASIC roadmaps for the development of advanced packaging technologies (SMT, solder ball attach, and other assembly process) • Participate early in Si/package/PCB/system co-design and ODM SMT manufacturing work in product development design reviews, providing feedback on manufacturability and helping incorporate the latest technology advancements and design rules • Create, conduct and analyze Design of Experiments (DOE) for development and sustaining activities • Work cross-functionally with design, NPI, quality and reliability, and manufacturing teams, and support new technology integration into products • Support selection and qualification of external partners (ODM, OEM, OSAT) • Collaborate with internal and external stakeholders to ensure seamless integration of packaging technology into product development cycles • Stay abreast of the latest advancements in advanced packaging technologies and market trends • Identify and evaluate emerging technologies with potential for future applications • Ability to travel internationally, typically once per quarter Minimum Qualifications • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience • Master's degree in Materials Science, Mechanical Engineering, Electrical Engineering, or a related field, or equivalent practical experience • 8+ years of experience in semiconductor packaging with direct ownership of advanced packaging development and assembly process and manufacturing • In-depth knowledge of flip chip, 2.5D and 3D packaging technologies • Experience taking products from concept to production, including development of manufacturing specifications, vendor qualifications, and improvement of manufacturing efficiencies and costs • Experience communicating technical packaging decisions in writing and in reviews to cross-functional engineering and manufacturing stakeholders • Experience working effectively with cross-functional teams • Willingness to travel internationally, typically once per quarter Preferred Qualifications • Experience working with ODM, assembly packaging, OSAT, and foundry partners • Knowledge of packaging and assembly industry standards • Proven understanding of fanout advanced packaging technologies • Hands-on experience in interposer or fanout package design for both organic and inorganic interposer with or without bridges such as CoWoS-L, CoWoS-R, EMIB, embedded fanout bridge from OSAT • Proven technical understanding of the full range of semiconductor packaging design, SMT processes, PCB design and layout tools, failure mechanisms and analytical techniques • In-depth knowledge of 2.5D and 3D packaging technologies, including silicon interposers, TSVs, and microbumps and advanced packages interaction with board-assembly constraints • Master's degree or PhD in Materials Science, Mechanical Engineering, or a related discipline