Senior Staff Device Design & Integration Engineer

The GaN Technology Development Group is seeking a Senior Staff Device Design and Integration Engineer for development and integration of next-generation technology platforms. This role will work across device design, process integration, product, test, reliability, and manufacturing teams to deliver technologies from concept through qualification and production. Key Responsibilities • Device architecture, design, and integration for next-generation technology platforms, balancing performance, cost, manufacturability, and reliability. • Define device and product requirements with product, applications, process integration, test, reliability, and manufacturing teams. • Drive chip design and layout, including active-cell, termination, metal interconnect, pad, and floorplan optimization. • Plan and support engineering and qualification lots, including characterization, DOE, reliability, and qualification activities. • Analyze electrical, yield, reliability, and qualification data and drive design or process improvements. • Lead root-cause analysis and corrective actions for performance, yield, quality, and reliability issues. • Provide technical leadership, communicate risks and decisions, and mentor engineers across cross-functional teams. Qualifications • PhD with 5+ years or MS with 8+ years of semiconductor device or product development experience in Electrical Engineering, Applied Physics, Materials Science, or a related field. • Strong knowledge of power-semiconductor device physics, chip layout, electrical characterization, and technology integration. • Experience taking semiconductor technologies or products from definition through engineering lots, qualification, and manufacturing release. • Experience analyzing characterization, yield, and reliability data using JMP, Python, MATLAB, or equivalent tools. • Strong cross-functional collaboration, technical leadership, problem-solving, and communication skills. Preferred Qualifications • Experience with GaN and/or silicon power devices, high-voltage design, termination, and interconnect optimization. • Knowledge of TCAD or compact modeling, DOE methods, process integration, and failure analysis. • Experience with JEDEC qualification and familiarity with AEC-Q101 requirements. Additional Information The expected annual pay range for this position is $145,000 - $181,000. This position is also eligible for bonus opportunities. Please note that final offer amount will be dependent on geographic location, applicable experience, and skillset of the candidate. Renesas offers a full range of elective benefits including medical, health savings account (with applicable medical plan), dental, vision, health and/or dependent care flexible spending accounts, pre-tax commuter benefits, life insurance, AD&D, and pet insurance. In addition to elective benefit options, benefited employees receive company-paid life insurance and AD&D, LTD, short term medical benefits as well as paid sick time, paid holidays, and accrued paid vacation. New employees will attend a detailed benefit orientation to learn more about our many benefits and resources. Videos To Watch https://www.youtube.com/embed/k-zs4tB6nNc