10+ years of hands-on custom IC layout experience, including 5+ years in SRAM or memory IP layout.
Direct execution of custom digital SRAM layout required; oversight experience is insufficient.
Hands-on experience at TSMC 3nm or more advanced process nodes; 10nm or 7nm experience is inadequate.
Solid understanding of SRAM and memory layout principles.
Extensive experience with Cadence Virtuoso for custom layout creation.
Proficient in DRC/LVS debugging using Calibre, ICV, or similar tools.
Familiarity with advanced-node layout limitations and layout-dependent phenomena.
Responsibilities
Manage the complete custom layout process for SRAM bitcell arrays and memory macros.
Develop and improve floorplans for SRAM and memory blocks, including power grid design and routing.
Conduct DRC, LVS, ERC, and other physical verification checks using tools like Calibre.
Support EM/IR review and ensure compliance with power integrity and DFM requirements.
Collaborate with circuit designers to convert schematics into layouts while maintaining reliability constraints.
Work with PnR and integration teams to resolve top-level DRC/LVS and routing issues.
Implement and advance layout methodology and quality standards for memory IP delivery.
Mentor junior engineers and enhance layout quality across the team.
Benefits
Opportunity to work on cutting-edge technology at advanced process nodes.
Collaborative environment with cross-functional teams.
Mentorship opportunities to guide junior engineers.
Focus on individual contribution rather than management, allowing for deep technical engagement.
Full Job Description
Role Overview We are seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies at the leading edge of process scaling. This is a senior individual-contributor role - youll own and contribute blocks alongside an established team of leads, not manage one. The role works closely with circuit design, PnR/integration, CAD, and foundry teams to deliver consistent, high-quality memory IP on advanced FinFET/GAA nodes, and includes reviewing layouts and mentoring junior engineers to raise layout quality and execution rigor across the team.
Key Responsibilities
Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
Required Qualifications
BSEE or equivalent experience.
10+ years of hands-on custom IC layout experience as a senior individual contributor (this is not a lead/people-management role), including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
Hands-on, personal ownership of custom digital SRAM layout - candidates must have directly executed the layout themselves, not simply overseen or reviewed it. This role is not a fit for mixed-signal or analog layout backgrounds.
Hands-on experience at TSMC 3nm or a more advanced process node. Experience limited to 10nm or 7nm does not meet the bar for this role; 5nm is a plus, but 3nm is the minimum.
Solid grasp of SRAM and memory layout principles.
Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
Preferred Qualifications
Background at TSMC, Intel, Samsung, or Micron (foundries or memory companies with their own advanced process nodes) is strongly preferred - TSMC alumni in particular.
Experience on TSMCs next-generation, beyond-3nm process nodes.
Knowledge of, or demonstrated motivation to learn, AI-assisted layout automation tools.
