Job Description:

Division: Microchip Data Center Solutions Business Unit

Location: Burnaby, BC, Canada

The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry's cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world's information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry's technology leadership.

As a Senior Engineer I-Design , your job will be contributing to the following areas under guidance of experienced leaders in product development field:

• Design of complex digital integrated circuits at the block, subsystem or device level (100K to 50M+ gates), which are coded in Verilog, System Verilog
• Define subsystem/block feature sets, describe design and implementation details into engineering documents and registers documents
• Support emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds
• Communicate regularly with the design and verification team in multiple locations to resolve issues, communicate status and solve technical problems
• Communicate with architects to justify design implementation decisions and associated trade-offs

Read and understand applicable storage and computer interface protocol standards

Requirements/Qualifications:

Qualifications/Requirements

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or equivalent
• 3 to 5 years related experience
• RTL Design - Experience in RTL Design using System Verilog, Verilog is required.
• Experience and understanding of complex ASIC design flows, including block and chip level simulation and debug, logic synthesis, static timing analysis, layout and revision control
• Experience with Formal Verification will be an asset.
• Working knowledge of design and verification tools such as Synopsys Design Compiler, Cadence Incisive, waveform viewers, and other similar tools.
• Scripting and programming skills using csh, bash, perl, python, tcl, etc will be an asset.
• Protocol knowledge and experience in PCI-Express will be an asset
• Knowledge of AHB/AXI bus protocols is desired.
• Knowledge in logic synthesis and static timing analysis.
• Worked with physical design teams for layout implementation. Familiar with low power methodology and flows.
• Excellent analytical and debugging skills and the ability to proactively solve issues
• Good verbal and written communication skills in English will be an asset
• Excellent teamwork and time management skills, self-direction, the ability to work under pressure and the desire to excel in a competitive environment

Travel Time:

0% - 25%

Pay Range:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:

Benefits of working at Microchip

The annual base salary range for this position is $86,000-$186,000.*

*Range is dependent on numerous factors including job location, skills and experience.

To all recruitment agencies: Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.