Arista Networks

Senior Signal Integrity / Power Integrity (SI/PI) Engineer

Arista Networks$300K — $500K+*
Telecommunications & Hardware
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • BS/MS/PhD in Electrical Engineering, Physics, or related field focusing on electromagnetics or high-speed digital design.
  • Solid understanding of signal integrity theory and S-parameter analysis.
  • Hands-on experience with 2.5D/3D EM solvers like Ansys HFSS or Sigrity.
  • Strong lab skills in using oscilloscopes, VNAs, and TDRs.
  • Familiarity with advanced PCB materials for high-speed design.

Responsibilities

  • Perform 3D EM design and simulation for high-speed interconnects using advanced tools.
  • Develop test vehicles for characterizing PCB materials and interconnects.
  • Conduct measurements to validate modeling and extract channel performance.
  • Analyze link-level performance for advanced standards using simulation tools.
  • Collaborate with teams to optimize designs for high-density applications.
  • Research novel materials and topologies to achieve next-gen performance.
  • Support production board bring-up and debug cross-functional SI/PI issues.

Benefits

  • Medical, dental, and vision coverage.
  • Wellbeing programs and tax savings options.
  • Income protection plans.
Full Job Description
Job Description

Who You'll Work With

Arista's cutting-edge Ethernet and optical networking platforms are built to push the limits of performance, density, and power efficiency. This wouldn't be possible without our Signal Integrity (SI) and Power Integrity (PI) engineers who design, simulate, and characterize interconnects enabling the fastest SerDes technologies in the industry. We're looking for a Senior Signal Integrity / Power Integrity Hardware Engineer to join our Hardware Design team at our headquarters in Santa Clara, CA. In this role, you'll work at the intersection of advanced simulation, next-generation SerDes (112G/224G/448G PAM4), and innovative routing, packaging, and power delivery techniques. Your work will directly influence the architecture and layout of Arista's next-generation Ethernet and optical systems for hyperscale, AI, and cloud networking.

The total estimated annual compensation range for this position, inclusive of base salary, bonus, and equity, is $300,000 to $655,000. This range is a good faith estimate only. Bonus and equity are discretionary, subject to plan terms, and are not guaranteed components of total compensation. Actual total annual compensation may vary based on employee performance, company or equity performance, company policy, board approval, or similar factors. Please see additional base salary information below.

What You'll Do
  • Perform 3D EM design and simulation of high-speed interconnects (channels, vias, packages, and connectors) for 112G/224G PAM4 SerDes using tools such as Ansys HFSS, SiWave, and Cadence Sigrity.
  • Develop and validate test vehicles to characterize next-generation PCB materials, packages, and interconnects.
  • Conduct S-parameter and time-domain measurements (VNA, TDR, BERT) to extract channel performance and validate modeling correlation.
  • Perform link-level analysis for advanced standards (Ethernet 800G/1.6T, PCIe Gen6/Gen7, CXL) using tools such as Keysight ADS or Cadence SystemSI.
  • Collaborate closely with hardware, mechanical, and packaging teams to optimize stack- up, breakout, and routing strategies for high-density designs.
  • Research and prototype novel materials, backplane concepts, and low-loss interconnect topologies to meet next-generation performance targets.
  • Support bring-up and debug of production boards, working cross-functionally to root-cause SI/PI issues.


Qualifications
  • BS/MS/PhD in Electrical Engineering, Physics, or related field with a focus on electromagnetics, signal integrity, or high-speed digital design.
  • Solid understanding of signal integrity theory, S-parameter analysis, and channel modeling.
  • Hands-on experience with 2.5D/3D EM solvers (Ansys HFSS, SiWave, Sigrity, CST).
  • Strong lab skills using oscilloscopes, VNAs, TDRs, BERTs, and Ethernet compliance tools.
  • Familiarity with advanced PCB materials (e.g., Megtron 7, Tachyon 100G, SLP) and manufacturing constraints for high-speed design.
  • Experience analyzing and simulating 56G/112G/224G PAM4 and NRZ serial links.
  • Knowledge of power integrity and co-simulation techniques is a plus.
  • Excellent communication and collaboration skills.

Preferred Qualifications
  • Experience with co-packaged optics, chiplet-based architectures, or advanced substrate technologies.
  • Familiarity with EMI/EMC considerations and signal/power isolation in densely integrated photonic-electronic systems.
  • Understanding of thermal and mechanical effects on SI/PI performance and long-term reliability.
  • Experience working with fabrication vendors, ASIC teams, and contract manufacturers to ensure end-to-end channel integrity.

Base Salary Information:

The new hire base pay for this role has a pay range of $180,000 to $275,000. Arista offers different pay ranges based on work location, so that we can offer consistent and competitive pay appropriate to the market. The actual base pay offered will be based on a wide range of factors, including skills, qualifications, relevant experience, and work location. The salary range provided reflects base pay only. As described above, this position may also be eligible for discretionary Arista bonuses and equity. US- based employees are also entitled to benefits including medical, dental, vision, wellbeing, tax savings and income protection. The recruiting team can share more details during the hiring process specific to the role and location.

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About Arista Networks

Arista Networks is a computer networking company headquartered in Santa Clara, California. The company designs and sells multilayer network switches to deliver software-defined networking solutions for large datacenter, cloud computing, high-performance computing and high-frequency trading environments. Arista Networks was founded in 2004 by former Cisco Systems engineers and is led by CEO Jayshree Ullal. The company went public in 2014 and is traded on the New York Stock Exchange under the ticker symbol ANET.
Learn more about Arista Networks
Size
2,993 employees
Market Cap
$36.5 billion
Industry
Net Income
$634.5 million
Founded
2004
5 Year Trend
+21.2%
Revenue
$2.3 billion
NASDAQ

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