We are looking for a Senior Design Engineer to design, integrate, and sign off RTL for blocks across our power-efficient SoC: the compute fabric's on-chip interconnect and memory interfaces, low-power and always-on logic, and standard peripheral IP (RISC-V, NVM, I2S, I2C). As a hands-on individual contributor, you will take blocks from microarchitecture spec through clean, synthesis-ready RTL, working closely with architects, the design lead, DV, physical design, and firmware to tape out an industry-leading ultra-low-power SoC.
This is a unique opportunity to join a growing HW engineering org early and leave your mark on our products and processes as we move from initial product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!
Key ResponsibilitiesRTL Design & Integration- Implement microarchitecture and RTL for assigned blocks in the compute fabric, on-chip networks/NoC, memory interfaces, and peripheral subsystems, working from architecture and uArch specifications.
- Integrate third-party and in-house IP (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C/APB peripherals) at the subsystem and SoC level, including bus fabric hookup and memory-mapped register interfaces.
- Write and maintain uArch and design documentation for your blocks; present them in design reviews with architecture, DV, and physical design.
Front-End Design Flows & Sign-off- Own block-level front-end quality: lint-clean RTL, CDC and RDC analysis with waivers reviewed and documented, and LEC between RTL and netlist.
- Run synthesis, write and maintain SDC timing constraints, and analyze STA reports; iterate on RTL to meet timing, area, and power targets.
- Drive issues to closure with physical design during timing and congestion closure.
Low-Power Design- Implement low-power RTL per UPF intent: power domains, isolation, level shifters, retention, and fine-grained clock gating.
- Contribute to PMU and always-on (AON) logic, such as power sequencing state machines and wakeup event aggregation.
- Ensure clock-gating enables are timing-clean and CDC-correct; run RTL power analysis and act on the results.
Verification Support & Debug- Run block-level simulations and debug failures alongside the DV team; contribute directed test scenarios for corner cases, back-pressure, and power-state transitions.
- Run and debug gate-level simulations.
- Support silicon bring-up with RTL-level debug during lab validation.
Required Qualifications & Experience- 8-10 years of front-end digital design experience on processor, accelerator, or SoC products.
- Significant contributions to at least two tapeout cycles.
- Strong proficiency in SystemVerilog for synthesizable RTL: state machines, arbiters, FIFOs and flow control, and datapath logic.
- Hands-on experience with standard VLSI front-end flows: lint, CDC/RDC, LEC, synthesis, SDC constraints, and STA, with the ability to interpret and act on their reports.
- Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, isolation, and retention.
- Working knowledge of at least one on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL level.
- Experience with on-chip memories: SRAM wrappers, banking, and memory-mapped register interfaces.
- Comfortable running RTL simulations and debugging with waveform tools.
- Clear written and verbal communication; able to document designs and hold design reviews.
Desired Qualifications & Experience- Experience designing or integrating on-chip networks, dataflow pipelines, or memory subsystems.
- Familiarity with NVM controller RTL (MRAM, RRAM, etc.), including ECC and program/erase sequencing.
- Experience with very low power design techniques and the RTL design choices they require.
- Understanding of parallel execution models such as dataflow, SIMD, or systolic arrays.
- Experience with RTL and gate-level power analysis tools and methodologies.
- Exposure to DFT concepts: scan insertion, ATPG, and DFT-friendly RTL coding.
- Scripting skills (Python, Tcl, Perl) to automate design flows.
We offer a competitive base salary for this role, generally ranging from $180,000 to $245,000, plus a 10% annual bonus, meaningful equity, and comprehensive benefits. Final compensation will depend on experience, level, and location, with flexibility for the right candidate.
