Senior Principal Engineer Digital ASIC Design (RFIC5395) Exempt: Yes Safety Sensitive: No Department: TUBIS Reports To: Not indicated GENERAL DESCRIPTION OF POSITION Responsible for architecture of digital design. Plan and implement digital infrastructure. Plan, oversee, and execute implementation, verification, emulation, and validation of design. Identify potential high-risk areas and present possible resolutions. Drive methodology process and requirement specification documents. Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules. ESSENTIAL DUTIES AND RESPONSIBILITIES 1. Lead digital design projects from inception to production for mixed signals ICs. 2. Hire and manage full-time employees or contractors to support projects. 3. Participate in RFIC design flow by architecting and designing digital control functionality which interfaces to I/O and analog functions. 4. Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions. 5. Perform project resource planning, detailed schedule development, milestone and task tracking 6. Oversee PNR and ensure integrity of physical layer design. 7. Perform/oversee test plan development, digital verification, coverage analysis, and post silicon lab test. 8. Support mixed signal verification of design. 9. Perform/oversee scan insertion, MBIST and LBIST. 10. Perform any other related duties as required or assigned. REQUIREMENTS/QUALIFICATIONS - BS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1st silicon success - Proven technical leadership experience - Ability to work with cross-functional teams and contractors across geographical boundaries - Strong verbal, communication and organizational skills - Ability to improve digital design methodology to deliver high quality ICs on schedule - Experience with requirements development, design reviews and documentation - Experience with mixed-signal design methodology - System level experience with architectural tradeoffs for partitioning functions across software, embedded firmware, and custom RTL based hardware accelerators. - Experience with architectural tradeoffs for selecting/defining high-speed communication interfaces - Experience with the selection and integration of embedded processor cores (RISC-V or similar), memory systems, priority interrupt controller, etc. - Ability to perform area and power estimation - Experience with test plan development for pre-silicon verification/emulation and post silicon validation - Solid understanding of DFT architecture and familiarity with production test methods - In depth knowledge and extensive hands-on experience in digital RTL design (Verilog/System Verilog) and micro-architecture, linting, LEC, RDC/CDC, SDF gate simulation, revision control and tagged releases, scripting, bug tracking, synthesis, scan insertion, timing constraint development, floor planning, clock tree synthesis, timing closure, netlist ECOs, and digital verification. - Experience with foundry provided CMOS process and design kits, standard cell libraries and memory compilers - Experience setting up toolchains (compiler, debugger, etc.) for embedded processor cores - Experience developing embedded firmware (C and assembly language) for embedded processor cores for digital verification - Experience with co-simulation to verify debug interface operability with the tool chain - Experience with Synopsys and Cadence front-end and back-end tools, such as: Xcelium, Genus, Conformal, Innovus, Synopsys PrimeTime, Spyglass Lint, TetraMax - Ability to perform/oversee post silicon bench test of digital functions - Experience with UVM is a plus - Experience with digital design for PLL control/calibration is a plus Experience with interfacing to ADC/DAC, trim/calibration algorithms and DSP is a plus ADDITIONAL INFORMATION The above statements are intended to describe the work being performed by people assigned to this job. They are not intended to be an exhaustive list of all responsibilities, duties and skills required. The duties and responsibilities of this position are subject to change and other duties may be assigned or removed at any time. This position may require exposure to information subject to US export control regulations, i.e. the International Traffic in Arms Regulation (ITAR) or the Export Administration Regulations (EAR).