The Role
As a Senior Modem ATE Test Engineer, you will engage with an experienced cross-disciplinary staff to conceive and design innovative product solutions for custom silicon powering the Leo network. You will lead the development of high-volume production test methodology for complex SoCs and modem devices, working closely with internal inter-disciplinary teams and third-party suppliers to drive key aspects of test definition, execution, and optimization.
You will own digital ATE test development end-to-end on Advantest 93K and/or Teradyne UltraFLEX platforms, from bring-up and pattern conversion through characterization, correlation, and production release. You will develop and debug structural and functional test content including scan/ATPG, MBIST and memory repair, and other DFT-based tests, as well as high-speed SERDES/HSIO test for complex modem and/or ASIC/SoC devices. You must be responsive, flexible, and able to succeed within an open, collaborative peer environment, and you will influence ASIC design, DFT, and manufacturing teams to ensure our products are architected for testability and cost-effective high-volume manufacturing.
Export Control Requirement
Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.
Key job responsibilities
In this role you will:
• Develop, debug, and release digital test programs for complex ASIC/SoC and modem devices on Advantest 93K and/or Teradyne UltraFLEX platforms.
• Build and debug scan/ATPG test content (stuck-at, transition, and other fault models) for complex ASIC/SoC and modem devices.
• Implement MBIST and memory repair flows.
• Characterize silicon performance and process variation through ring oscillator and process monitor tests.
• Test and debug I/O interface such as I3C, SPI, and GPIO.
• Optimize high-speed SERDES/HSIO test, including equalization, jitter/eye characterization, BER, and loopback.
• Convert test patterns from the DFT team into tester-suitable formats (e.g., STIL/WGL to native tester formats) and validate them on hardware.
• Bring up and characterize new devices, define test conditions (timing and levels), and drive shmoo/characterization to establish robust production limits and guard bands.
• Lead device correlation between wafer sort and final test, resolving systematic offsets and measurement issues.
• Reduce test time and cost across digital and DC test content while maintaining test coverage and quality.
• Design and review final test (FT) and wafer sort (WT) hardware, including load board, socket, and probe card designs, for best layout practices and signal/power integrity, particularly for high-speed digital interfaces.
• Partner with ASIC design and DFT teams to ensure devices meet Amazon standards for design-for-test and design-for-manufacturability in advanced process nodes.
• Analyze production data using statistical methods (Cp/Cpk, yield analysis) to drive continuous improvement in yield, quality, and test efficiency.
• Actively identify test-related readiness gaps, issues, and optimization opportunities throughout the product lifecycle and drive them to resolution.
• Support qualification activities such as burn-in board design, HTOL, and ESD.
• Mentor and provide technical guidance to junior test engineers, lead technical reviews, and set best practices for the test development team.
BASIC QUALIFICATIONS
- Bachelor's degree or above in electrical engineering, computer engineering, or equivalent
- 7+ years of experience in digital ATE test development and test engineering, preferably in high-volume manufacturing.
- Experience testing complex SoCs and modem/wireless communication devices in advanced nodes (7nm and below).
- Experience developing and debugging test programs on Advantest 93K and/or Teradyne UltraFLEX platforms.
- Familiarity with JTAG and boundary-scan techniques, and with DFT/DFM principles.
- Experience with digital test methodologies such as scan/ATPG, MBIST, Vmin search, and loopback.
- Proficiency in advanced high-speed SERDES test at 100G+, including equalization tuning and jitter decomposition.
- Experience with wafer sort and final test ATE hardware development, bring-up, and debugging.
- Strong written and verbal communication skills.
- International travel required during release-to-production phases.
PREFERRED QUALIFICATIONS
- Master's degree in Electrical/Computer Engineering.
- Demonstrated ability to lead cross-functional technical efforts and mentor other engineers.
- Experience running firmware on DUTs to reduce test time and increase self-testability.
- Working knowledge of PLL test and characterization (lock time, jitter, loop bandwidth).
- Understanding of standard silicon security concerns for these device types, such as secure boot, secure key/identity provisioning, and protection of sensitive assets during manufacturing and test.
- Experience with OTP/eFuse programming and qualification.
- Strong data analysis skills using statistical platforms (JMP, or similar), yield and process capability metrics, data interpretation, and bench/tester correlation
- Knowledge of PCB design requirements and layout best practices for high-speed signaling.
- Understanding of semiconductor manufacturing, assembly, and test processes in advanced nodes.
- Familiarity with production control processes.
- Working knowledge of scripting languages such as Python, Perl, and Tcl/Tk.
The base salary range for this position is listed below. Your Amazon package will include sign-on payments and restricted stock units (RSUs). Final compensation will be determined based on factors including experience, qualifications, and location. Amazon also offers comprehensive benefits including health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage), 401(k) matching, paid time off, and parental leave. Learn more about our benefits at https://amazon.jobs/en/benefits.
USA, CA, San Diego - 159,200.00 - 215,300.00 USD annually
USA, CA, Sunnyvale - 183,000.00 - 247,600.00 USD annually
USA, WA, Redmond - 159,200.00 - 215,300.00 USD annually
