Master's in Electrical/Computer Science Engineering with 3+ years, or Bachelor's with 5+ years of experience
Experience in RTL-to-GDS physical implementation
Deep understanding of EDA tools/design flows
Familiarity with TSMC N16 technology or better
Experience in block level design and chip integration
Proficient in Perl/TCL programming
Willingness to work onsite in North Austin, TX area
Responsibilities
Lead block-level and tapeout chip physical implementation
Analyze and optimize floorplan quality
Design customized clock tree structures and handle place & route
Implement ECOs to achieve timing closure
Conduct EM/Noise and Power IR analysis
Perform DRC/LVS/ERC/ANTENNA analysis
Finalize physical verification sign-off
Benefits
Comprehensive benefits package
Extensive development opportunities and training programs
Hybrid work schedule with 4 days in office
Commitment to diversity and inclusion in the workplace
Potentially access to cutting-edge semiconductor technologies and projects
Full Job Description
Overview of Role
As a Sr. Physical Design Engineer, you will be responsible for the entire APR implementation flow from RTL-to-GDS that includes synthesis, floorplan, place and route, CTS, STA, and signoff. You will be reporting to Manager of Advanced Chip implementation team at its Austin Design Center, Texas and joining a team of engineers dedicated to pushing the envelope for the world's leading semiconductor company. We are currently operating in a hybrid work schedule with 4 days in office.
Responsibilities
Complete entire physical implementation of the block level and tapeout production chip
Block level floorplan with the ability to analyze the quality of the floorplan
Customized Clock tree structure and Place & Route
Implement ECOs for timing closure
Signal EM/Noise and Power IR/EM analysis and fix
DRC/LVS/ERC/ANTENNA analysis and clean up
Physical verification sign off
Minimum Qualifications
Master's degree in Electrical/Computer Science Engineering with 7+ years of industry experience.
