Job Description:
Microchip is currently looking for a Senior Physical Design Engineer to join our Implementation team in our Burnaby BC office. As a key member of Microchip's Implementation team, the successful candidate will execute chip development methodologies which include block level place and route, physical design verification, macro level test structures, digital wrapper development for analog cells, synthesis, static timing for high-performance devices. The successful candidate will also work closely with our customers to support them through Microchip's Chip development flow, and work with other groups across disciplines (CAD, Packaging, Mixed Signal, Operations, and Design) to ensure the Chip is successfully completed. Our team uses state-of-the-art tools and flows to build large and complex SOCs/ASICs.
Requirements/Qualifications:
This position requires at least 4-year degree in Electrical or Electronics Engineering with 7.5+ years of ASIC development experience in a fast paced environment.
- Design, Synthesis, Static Timing and Place & Route experience in high performance design (high speed / low power) is a must. Advanced knowledge of semi-custom design & implementation tools
- Hands-on experience in all aspects of physical design flows such as floorplanning, placement optimization, clock tree synthesis and physical verification
- Recent experience with leading full chip Physical Design activities
- Implement chip level, subsystem, CPU, and mixed signal blocks.
- Excellent analytical and debugging skills and the ability to proactively solve issues.
- Ability to guide others based on changing priorities
- Proven ability to thrive on, learn and adapt to new methodologies and technologies
- Must be able to work autonomously, but ensure to inform management of current status.
- Be able to understand Verilog and VHDL languages
- Excellent oral and written communications skills.
- Experience with 6nm process or lower a plus
- Proficiency in Python/PERL/TCL scripting is essential
- Self-motivated team player that can collaborate with multiple teams across a geographically diverse company to achieve desired design goals is crucial
Travel Time:
0% - 25%
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:
The annual base salary range for this position is $86,000-$186000.*
*Range is dependent on numerous factors including job location, skills and experience.
