BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.
Strong understanding of digital design fundamentals, including FSMs and low-power design.
Expertise in Verilog, SystemVerilog, UVM/OVM, and class-based verification methodologies.
Hands-on experience developing testbenches, drivers, and reusable verification IP.
Proficiency in Python, Perl, and UNIX/Linux shell scripting for automation.
Experience using AI/LLM-based technologies to enhance engineering processes is preferred.
Responsibilities
Lead digital verification activities from planning through signoff.
Define and implement comprehensive verification plans and methodologies.
Review architecture specifications and product requirements critically.
Develop advanced verification environments, applying SystemVerilog, UVM, and assertions.
Create diverse test scenarios to validate digital PMIC functions.
Analyze and drive coverage closure and signoff metrics.
Mentor junior engineers while fostering cross-team collaboration.
Benefits
Opportunity to work on next-generation Power Management ICs for automotive and industrial sectors.
Engagement in a dynamic, global team focused on innovation and excellence.
Emphasis on continuous learning and professional development opportunities.
Potential to influence methodology improvements and automation in verification processes.
Full Job Description
Job Title: Senior Digital Verification Engineer
Primary Location: Chandler, Arizona, USA
Role Summary: The Advanced Power Systems group within NXP's Power and Energy Business Line is seeking a Senior Digital Verification Engineer to develop next-generation Power Management ICs (PMICs) for automotive and industrial applications. This role will lead digital verification from architecture review through verification signoff, ensuring functionality, quality, reliability, and compliance.
Job Responsibility:
Lead digital verification activities and drive successful project execution from planning through signoff.
Review product requirements, architecture specifications, microarchitecture, interfaces, and implementation plans.
Develop and maintain advanced verification environments using SystemVerilog, UVM, VIPs, scoreboards, monitors, checkers, and assertions.
Create directed and constrained-random test scenarios to validate functionality, performance, robustness, and corner-case behavior.
Define, implement, and analyze functional, code, and assertion coverage; drive coverage closure and signoff.
Apply SystemVerilog Assertions (SVA), formal verification methodologies, and regression analysis to identify and resolve issues.
Verify PMIC digital control, telemetry, diagnostics, safety, power sequencing, fault management, communication interfaces, and embedded control functions.
Deliver verification collateral including test plans, environments, assertions, regressions, coverage reports, metrics, milestones, and requirements traceability.
Drive methodology improvements, automation, reuse, and productivity while mentoring junior engineers and collaborating across global teams.
Job Qualification:
BSEE with 8+ years, MSEE with 5+ years, or PhD with 3+ years of semiconductor industry experience.
Strong understanding of digital design fundamentals, FSMs, CDC, reset architecture, low-power design, and SoC integration.
Expertise in Verilog, SystemVerilog, UVM/OVM, and class-based verification methodologies.
Strong knowledge of constrained-random, coverage-driven verification, regression automation, and verification signoff.
NXP Semiconductors N.V. is a Dutch semiconductor manufacturer with headquarters in Eindhoven, Netherlands. The company employs approximately 31,000 people in more than 35 countries, including 11,200 engineers in 33 countries. NXP reported revenue of $8.88 billion in 2020. The company's products are used in a wide range of automotive, identification, wireless infrastructure, lighting, industrial, mobile, consumer and computing applications. NXP is the co-inventor of near field communication (NFC) technology along with Sony and supplies NFC chip sets that enable mobile payments, as well as secure access to cars and buildings.
