The mixed-signal high-speed I/O group delivers innovative PHY designs that power the most powerful AI systems in the world today. Our portfolio includes PHY IPs and Chips for both copper and fiber channels, supporting NVIDIA's high-performance interconnect protocols: NVLINK, Ethernet, and InfiniBand. We recently delivered the industry's first 200G MRM-based silicon photonics chip, revolutionizing high-performance networking and enabling the era of Co-Packaged Optics (CPO) for NVIDIA. We enable groundbreaking technology that continually pushes the limits of wireline communication!
What You'll Be Doing:While engaged in frontend development, your responsibilities will include working on a wide range of high-speed, powerful DSPs, silicon photonics IPs, and chips. You will participate in chip-level features, programming model and application interface definitions. You will collaborate closely with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, which then will be translated into RTL and firmware designs. For backend design, you will define, build synthesis constraints and drive timing closure. Evaluating PPA trade-offs based on synthesis and P&R feedbacks is a critical step toward the most optimized product. For post-silicon, you will actively participate in silicon bring-up, build testing scripts for debugging, characterization, performance tuning, and production. You will also work with cross-functional teams to ensure successful production.
What We Need to See:- B.S. or M.S. degree in Electrical Engineering or equivalent experience.
- 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools.
- Deep understanding of Verilog or System Verilog, logic design concepts, and typical structures.
- Good understanding of design for test, timing constraints, and static timing analysis.
- Experience with industry verification methodologies, such as UVM.
Ways to stand out from the crowd:- Knowledge of optical transceiver devices and integrated components such as modulators, detectors, and TIAs.
- Experience with SerDes architecture and building blocks such as CDR, DFE, CTLE, TXFIR.
- Experience with digital assist analog designs, such as calibrations.
- Familiarity with mixed-signal circuit design concepts and experience in behavior modeling of mixed-signal circuits. Knowledge of physical layer and communication protocols, such as Ethernet, InfiniBand, PCIe, and USB.
- Understanding of on-chip microcontrollers and standard peripherals, with exposure to hardware and firmware co-design.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 12, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
