What you'll doAs a senior Design Verification Engineer, you will be part of a verification team responsible for the full cycle of RTL verification for FPGA and ASIC designs. You will be responsible for:
• Design verification planning including test plans
• Testbench development using SystemVerilog/UVM
• Hands-on debug with the design team
• Ensuring quality via collection and analysis of coverage metrics including code and functional coverage
• Managing regressions and compute resources
• Tool evaluation and license management
• Responsible for owning and driving technical issues to resolution
You will be working in a verification environment utilizing current tools and methodologies such as Universal Verification Methodology (UVM) and new DV AI agentic tools. You will be asked to help evaluate and deploy new technologies for design verification as they become available.
At Viasat, you will be joining a talented and motivated team of systems engineers, design engineers, and design verification engineers developing cutting edge communications technology with a focus on high quality and time to market.
This is a site-based role, employees work 3+ days (60%+) per week from a Viasat office or work location within a standard five-day workweek.
The day-to-day- Create drivers, monitors, scoreboards, sequences, and model predictors for a variety of interfaces and designs
- Maintaining and communicating program schedule and task tracking (Agile Jira based)
- Debugging failing tests, understanding both the UVM testbench and VHDL/Verilog source code, working closely with the RTL developers
- Running and analyzing regressions
What you'll need- Bachelor's Degree in Electrical Engineering, Computer Engineering or a related field
- 5+ years Design Verification experience including UVM testbench experience
- Foundational knowledge of digital logic and timing considerations
- Attention to detail, ability to follow process and coding guidelines, participate in code reviews and accept feedback
- Experience with industry standard simulators such as Questa, Xcelium, and VCS
- Proven track record of work in UVM testbench development
- Good oral and written communications skills
- US citizenship
- Ability to travel up to 10%
What will help you on the job- Strong written and verbal communication skills, ability to work with a geographically distributed team
- Object oriented programming experience
- Familiarity with designing and coding for testbench horizontal and vertical re-use
- Ability to work independently, take initiative, and take ownership of tasks and results
- Familiarity with CI/CD practices
- Familiarity with AI Agents (Claud Code, Copilot, etc.)
- Strong troubleshooting skills
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Salary range$132,500.00 - $209,500.00 / annually.For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $164,500.00- $246,500.00/ annually
At Viasat, we consider many factors when it comes to compensation, including the scope of the position as well as your background and experience. Base pay may vary depending on job-related knowledge, skills, and experience. Additional cash or stock incentives may be provided as part of the compensation package, in addition to a range of medical, financial, and/or other benefits, dependent on the position offered. Learn more about Viasat's comprehensive benefit offerings that are focused on your holistic health and wellness at https://careers.viasat.com/benefits.
