We are seeking a Senior ASIC Design Engineer to join our processor subsystem team, focused on the configuration, integration, and verification planning of Arm processor IP and associated subsystem components for satellite IoT connectivity ASICs. This role sits at the intersection of RTL design and functional verification, requiring a strong grasp of processor subsystem architecture and hands-on experience bringing together complex IP in a cohesive, validated design. We are looking for dedicated self-starters who thrive in a fast-paced environment, can take ownership of complex technical challenges, and drive them through to completion with minimal oversight.
Key Responsibilities:
• Configure and integrate Arm processor IP (e.g., Cortex-M series) and associated subsystem components including bus interconnects, memory controllers, and peripheral IP
• Define and implement subsystem-level RTL integration, ensuring correct connectivity, clocking, and reset architecture across all subsystem components
• Collaborate with SoC architects to translate subsystem requirements into a coherent RTL implementation
• Work closely with the verification team to define and develop comprehensive testplans covering subsystem functionality, processor interfaces, and IP integration
• Author and review design specifications and integration guides for the processor subsystem
• Identify and resolve integration issues across IP boundaries, including protocol, clocking, and reset domain crossings
• Support synthesis and timing closure for the processor subsystem in coordination with the physical design team
• Participate in design reviews and contribute to continuous improvement of design and integration methodologies
• Support bring-up and debug activities for the processor subsystem on post-silicon hardware
Required Qualifications:
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
• 7+ years of experience in ASIC/SoC design with a focus on processor subsystem integration
• Strong proficiency in RTL design and integration using SystemVerilog or VHDL
• Experience working with AMBA bus protocols (AHB, APB, AXI) in the context of subsystem integration
• Demonstrated experience collaborating with verification teams on testplan definition and functional coverage
• Familiarity with industry-standard EDA tools for RTL compile and simulation (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
• Familiarity with synthesis flows and static timing analysis in the context of processor subsystems
Preferred Qualifications:
• Experience with Arm Corstone or similar processor subsystem reference designs, including hands-on configuration and integration of Arm processor IP (Cortex-M series or similar)
• Knowledge of low-power design techniques and their application within processor subsystems
• Familiarity with Arm tools such as Socrates, Configuration Wizard, or similar IP configuration tools
• Experience with scripting languages (e.g., Python, Tcl, Perl) for design automation and EDA tool flows
• Experience with UPF-based power-aware design flows
• Background in satellite IoT, embedded communications, or similarly constrained application domains
• Experience with post-silicon bring-up and debug of processor subsystems
This is a full time, exempt position, based out of our Saratoga office. The target base pay for this position is $150,000 - $220,000 annually. The total compensation packaged will be determined by various factors such as your relevant job-related knowledge, skills, and experience.
We are redefining how satellites are designed, manufactured and used-so we're looking for candidates with passion, deep knowledge and direct experience on LEO satellite component development, design and in-orbit activities. If that's your experience - then we'll be immediately wow-ed.
E-Space is not currently able to provide employment sponsorship for candidates who do not hold work authorization for the location of this role
