RoleAs a Senior Analog Layout Designer, you will be working to create layouts for RX/TX lane macros and support lane-level integration.
Skills and Experience- 7+ years of Analog Layout Design experience
- Understanding of the Semiconductor Fabrication process and device/layout cross-sections
- Minimum 3 years of experience with the following TSMC FinFET processes: 2nm, 3nm, 4nm, 5nm
- Several tape-outs with FinFET processes, owning major layout macros (ADC, DAC, TIA, CDR, PLL, BGB, LDO)
- Expert-level knowledge of block/macro floor-planning, block integration, routing, clock distribution, and power grid implementation
- Expert-level knowledge of layout considerations for device matching, symmetry, parasitic reduction, and noise isolation
- Expert-level knowledge of running and debugging LVS/ERC/DRC/Density/DFM/Antenna verifications
- Expert-level knowledge of EM/IR analysis
- Expert-level knowledge of Cadence Virtuoso and Calibre/Pegasus verification tools
- Understanding of ESDs and Clamps, and their layout considerations
- Understanding of layout effects such as LOD/OSE/PSE/WPE/MBE/LDE
- Experience with lane integration and tape out versifications
- Experience working with revision-controlled design libraries
- Good communication skills
- Knowledge of SKILL, TCL, and Python scripting is a plus
Compensation & Equity- Competitive Salary: Commensurate with your experience, skills, and location
- Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it
- Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living-Local Bonus if your residence is within 20 minutes of the office
- Retirement Benefits: Employer-contributed retirement plans to help you build long-term financial security
