Role Overview
We are looking for talented RTL Engineers to help build Velaura's next-generation Physical AI SoC. In this role, you will work closely with architects, performance modelers, software engineers, verification engineers, and physical design teams to transform innovative architectural concepts into production silicon. You will own significant portions of the design, contribute to microarchitectural decisions, and help deliver high-performance, power-efficient hardware that enables the next generation of intelligent physical systems. We welcome engineers at all experience levels who are
passionate about building great hardware and solving challenging technical problems.
Responsibilities
• Design, implement, and optimize RTL for key portions of the Velaura SoC.
• Collaborate with architects to develop robust and efficient microarchitectures.
• Participate in hardware/software co-design discussions spanning AI workloads, memory systems, runtime software, and system architecture.
• Work with software teams to define hardware interfaces, execution flows, memory hierarchies, and performance-critical interactions.
• Contribute to compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, power-management logic, and other core SoC infrastructure.
• Optimize designs for performance, power, area, scalability, and reliability.
• Partner closely with verification and physical design teams throughout the development cycle.
• Analyze performance bottlenecks and propose architectural and implementation improvements.
• Leverage modern engineering tools, including AI-assisted development workflows, to improve productivity, quality, and design exploration.
• Participate in design reviews and contribute to a culture of technical excellence.
Required Qualifications
• Experience designing RTL for complex digital systems.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Experience with Verilog/SystemVerilog and modern RTL design methodologies.
• Familiarity with performance, power, and area tradeoffs.
• Understanding of memory systems, interconnects, caches, DMA engines, or accelerator architectures.
• Experience with hardware/software co-design and system-level performance optimization.
• Strong debugging and problem-solving skills.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.
Preferred Qualifications
• Experience with AI, machine learning, or edge AI hardware.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Knowledge of low-power design techniques and power management architectures.
• Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
• Experience using modern AI tools and workflows to accelerate engineering productivity.
• Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and advanced driver-assistance systems (ADAS),
aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.
$125,000 - $500,000 a year
Compensation & Benefits
At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a competitive base salary, performance-based incentives, and equity participation, allowing team members to share in the company's long-term success.
Your base pay will depend on your skills, qualifications, experience, and location.
In addition to compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well-being and growth of our team.
Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.
