5+ years of RTL design experience on chips that have taped out
Expertise in SystemVerilog/Verilog with strong microarchitecture skills
Hands-on experience with lint, CDC, synthesis, and timing-aware design
Familiarity with common protocols like AXI, PCIe, Ethernet, or DDR
Proficiency in Python or Tcl scripting
Responsibilities
Own microarchitecture and RTL implementation for IP blocks and subsystems
Drive designs through lint, CDC/RDC, synthesis, and timing closure
Partner with verification and formal teams on test plans and coverage closure
Debug complex functional and timing issues across simulation, emulation, and silicon
Review and evaluate AI-generated RTL for quality and correctness
Collaborate directly with customer design teams as needed
Benefits
Opportunity to work on real chip programs with leading semiconductor companies
Engagement with cutting-edge AI technology in design processes
Collaborative environment with cross-functional teams
Potential for professional growth in a rapidly evolving field
Hands-on experience with innovative design tools and methodologies
Full Job Description
About this Role
You'll design and own RTL for production silicon, from microarchitecture to signoff-ready code. You'll work on real chip programs with leading semiconductor companies while helping Voltai's AI learn to write, review, and debug RTL the way the best designers do.
What You'll Do
Own microarchitecture and RTL implementation for IP blocks and subsystems in SystemVerilog.
Drive designs through lint, CDC/RDC, synthesis, and timing closure with the backend team.
Partner with verification and formal teams on test plans, assertions, and coverage closure.
Debug complex functional and timing issues across simulation, emulation, and silicon.
Review and evaluate AI-generated RTL, and help define what correct, high-quality design looks like.
Work directly with customer design teams when needed.
What We're Looking For
5+ years of RTL design experience on chips that taped out.
Expert SystemVerilog/Verilog and strong microarchitecture skills.
Hands-on experience with lint, CDC, synthesis, and timing-aware design.
Familiarity with common protocols (AXI, PCIe, Ethernet, DDR, or similar).
Python or Tcl scripting.
Bonus Points
Experience writing SVA or working with formal verification.
