5-7 years of experience in semiconductor design and verification
Proven track record in training language models or foundation models
Strong understanding of design scaling laws and compute optimization
Experience in generating synthetic design data for hardware applications
Familiarity with evals that relate to design performance metrics
Responsibilities
Train AI models to specialize in semiconductor design and verification
Develop synthetic design data generation methods
Implement model distillation for efficient reinforcement learning
Collaborate with hardware engineers and RL researchers for design guidance
Build tools for enhanced model-driven design intelligence
Benefits
Work with a prestigious and experienced team including Olympiad medalists
Collaboration opportunities with industry leaders and top academia
Access to cutting-edge technology and resources
Engagement in innovative projects at the forefront of AI and hardware
Strong backing from Silicon Valley investors
Full Job Description
Mid Training
You will train frontier models to become highly knowledgeable semiconductor design and verification experts that serve as the foundation for reinforcement learning and automated chip development. You will develop methods for generating and curating synthetic design data, performing model distillation, and enabling continual learning at scale. You will work closely with hardware engineers, RL researchers, and verification specialists to create evals that guide design data quality and model improvement. You will collaborate with compute engineers to scale efficient training across thousands of GPUs and RL environments. You will build high-performance tools to investigate how data and simulation shape model-driven design intelligence.
You might thrive in this role if you have experience with
Training LLMs or foundation models on semiconductor design and verification corpora (e.g., RTL, netlists, PDKs, simulation logs)
Modeling design scaling laws and optimizing compute budgets for chip-design-specific workloads
