Product Engineer (Yield & Quality)

Taiwan Semiconductor Manufacturing Company Limited

$100K — $130K *
Manufacturing & Automotive
Less than 5 years of experience
Job Overview by Ladders

Qualifications

  • Master's Degree in Electrical Engineering required
  • Ability to travel and train in Taiwan for 6-9 months
  • Working knowledge of semiconductor physics and CMOS device operation preferred
  • Familiarity with digital circuit design preferred
  • Strong problem-solving and communication skills
  • Capacity to work under pressure in cross-functional teams
  • Dedicated to active learning and mission orientation

Responsibilities

  • Lead root cause analysis for N5/N4 chip performance issues
  • Analyze CP test bin and data logs to identify failure modes
  • Conduct electrical and physical failure analysis
  • Collaborate with Fab and process teams to define corrective actions
  • Implement action plans and verify their effectiveness
  • Provide early-stage design support to ensure smooth product tape-out
  • Review design rules and layouts to enhance manufacturing robustness
  • Characterize yield windows and identify optimal device performance conditions

Benefits

  • Opportunity to work in a cutting-edge 5-nanometer fab
  • Engagement with a culture centered around integrity and innovation
  • Involvement in impactful projects that affect millions of lives
  • Professional growth through training opportunities in Taiwan
  • Contribution to cross-functional team dynamics and solutions for quality issues
Full Job Description
Company

TSMC Arizona Corporation

Location

USA-Arizona

Posted

Jan 09, 2026

Product Design Engineer, Yield & Quality

TSMC Arizona is looking for Product Design Engineers to join our 5-nanometer fab, located in sunny Phoenix, Arizona. As a Product Engineer, you will demonstrate a strong sense of reliability and enthusiasm and will possess an attitude that embodies our core values - Integrity, Commitment, Innovation and Customer Trust.

TSMC Arizona's Product Designer is responsible for early-stage design, yield window performance, and identify root cause for chip performance.

Job Description:
  • Lead team to identify root cause for N5/N4 chip performance / yield / quality issues:
  • Analyze CP test bin / data log to identify failure mode
  • Electrical failure analysis and physical failure analysis to locate suspect process stage
  • Work with Fab integration team or process team to define corrective actions / solutions
  • Trace action implementation to verify effectiveness
  • Product early-stage design support to help product tape-out smoothly and Si success:
  • Design rule review & assessment for robust product design
  • Layout review or DFM to enlarge manufacturing window
  • Yield window characterization and device sweet spot identification for the best yield / performance process condition.


Minimum Qualifications:
  • Applicants must be legally eligible to work in the United States and have:
  • The ability to travel and train in Taiwan for 6 - 9 months
  • Master's Degree in Electrical Engineering, required
  • Working knowledge of semiconductor physics, CMOS device operation, and advanced semiconductor manufacturing is preferred
  • Familiar with digital circuit design is preferred.
  • Able to work within cross-functional teams.
  • Consistent problem-solving skills, communication abilities, and active learning
  • Able to work under pressure and mission orientation


Work Location: Phoenix, AZ

Training Location: Phoenix

Travel Percentage: As Required

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